Stress In Solder Joints Research Articles

Reliability analysis and optimization of BGA solder based on finite element simulation

Abstract For the reason of reliability improvement of BGA solder, ANSYS is used to establish a BGA solder model that contains information such as size, material, grid, etc. The thermal stress of solder is selected as the optimization objective by the optimization parameters of solder height, solder radial direction, and spacing of solder. Response surface methodology is used to design 17 sets of different level parameters for simulation calculations, and a regression equation between solder joint stress and optimization parameters is established to obtain the parameter combination with the minimum stress of solder. The analysis results show that the corner solder far from the chip are critical solder joint for failure. The optimized solder joint parameters are as follows. The solder height is 0.5 mm, the solder radial is 0.6 mm, and the solder spacing is 1 mm. The optimized solder joint stress value is 30.818 MPa, which reduces the stress by 27.71% compared to before optimization, which achieved the reliability improvement of BGA solder.

Thermal fatigue life prediction of Ag-2.5Sn solder joint in flip chip

The heat dissipation needs of high-power devices cannot now be met by traditional packing solders due to the fast development of microelectronics interconnect technology. In addition to having outstanding thermal and electrical conductivity, nano-silver-tin paste better satisfies the needs of electronic devices. Studying the thermal reliability of solder joints is extremely important, this article investigates the fatigue life of the nano-silver-tin solder joints in temperature cycling experiments. Based on the life test results, the thermal cycling fatigue life of the nano-silver-tin solder joint is determined to be 2880 cycles. Finite element software was used to replicate the chip’s bonding process and assess the solder joint stress and strain distribution. The stress and strain of nano-silver-tin solder connections under thermal cycling load are accurately modeled using the Anand viscoplastic model and elastic model. The findings indicate that the contact region between the solder connections and copper columns is where the chip generates the most stress and strain. The fatigue life of the solder joint is estimated by using the Coffin–Manson modified equation, and this prediction aligns closely with the experimental results.

A novel approach of fatigue testing and evaluation of electronic systems based on phase tracking

This paper presents an experimental approach to perform fatigue testing of a lightly damped electronic assembly subjected to harmonic excitation. By leveraging the power of the phase locked loop control algorithm, our proposed work aims to accurately track the phase of the system. This innovative approach enables precise measurement of the drop in resonant frequency due to fatigue, enhancing overall damage prediction. The proposed approach exploits the characteristics of the materials that the phase at the resonance is constant and for a lightly damped system, the value is close to pi/2. In the event that the test article experiences fatigue, and the resonant frequency undergoes a change, the controller will promptly adapt to the new frequency while upholding a constant phase, ensuring the uninterrupted continuity of the testing process. The proposed approach is demonstrated by using the Ball Grid Array (BGA) electronic package as an example, where the test setup, data acquisition, and data monitoring for identifying the interconnect failure are presented. Failure analysis of the test article shows that the primary failure mode is the solder joint failure at the Intermetallic (IMC) layer. A finite element model is developed and correlated with experimental modal analysis to accurately estimate maximum stress and deflection in solder joints. By utilizing the obtained results, one can create a more accurate SN curve for the tested material. This will allow for a better understanding of the material's fatigue behavior and enable more precise predictions of its durability in real-world applications.

Numerical investigation of thermal fatigue crack growth behavior in SAC305 BGA solder joints

PurposeThis study aims to investigate the reliability issues of microvoid cracks in solder joint packages exposed to thermal cycling fatigue.Design/methodology/approachThe specimens are subjected to JEDEC preconditioning level 1 (85 °C/85%RH/168 h) with five times reflow at 270°C. This is followed by thermal cycling from 0°C to 100°C, per IPC-7351B standards. The specimens' cross-sections are inspected for crack growth and propagation under backscattered scanning electronic microscopy. The decoupled thermomechanical simulation technique is applied to investigate the thermal fatigue behavior. The impacts of crack length on the stress and fatigue behavior of the package are investigated.FindingsCracks are initiated from the ball grid array corner of the solder joint, propagating through the transverse section of the solder ball. The crack growth increases continuously up to 0.25-mm crack length, then slows down afterward. The J-integral and stress intensity factor (SIF) values at the crack tip decrease with increased crack length. Before 0.15-mm crack length, J-integral and SIF reduce slightly with crack length and are comparatively higher, resulting in a rapid increase in crack mouth opening displacement (CMOD). Beyond 0.25-mm crack length, the values significantly decline, that there is not much possibility of crack growth, resulting in a negligible change in CMOD value. This explains the crack growth arrest obtained after 0.25-mm crack length.Practical implicationsThis work's contribution is expected to reduce the additional manufacturing cost and lead time incurred in investigating reliability issues in solder joints.Originality/valueThe work investigates crack propagation mechanisms of microvoid cracks in solder joints exposed to moisture and thermal fatigue, which is still limited in the literature. The parametric variation of the crack length on stress and fatigue characteristics of solder joints, which has never been conducted, is also studied.

Optimal Design of Thermal Cycling Reliability for Plastic Ball Grid Array Assembly Via Finite Element Method and Taguchi Method

Abstract A finite element simulation analysis model was developed for a plastic ball grid array (PBGA) assembly to analyze its behavior under thermal cyclic loading conditions. The stress distribution in the SAC305 solder joints at different locations within the array was investigated by using ANAND constitutive equations. Subsequently, the thermal fatigue life of the key solder joints was quantified. The study also examined the influence of the solder joint diameter, substrate thickness, solder joint height, printed circuit board (PCB) thickness, and mold compound height on solder joint stress. Optimization of assembly parameters was achieved through the application of the Taguchi method. An extensive analysis was conducted using different assembly parameter combinations, employing the L9(34) orthogonal array design to explore the thermal cycling effects. The computed average Von Mises stress Δσ for the critical thin-layer elements of solder joints located in hazardous positions within the assembly was notably affected by variations in the solder joint height, substrate thickness, solder joint diameter, and mold compound height. This impact ranked in descending order of significance as solder joint height, substrate thickness, solder joint diameter, and mold compound height. The optimal parameter combination determined was a solder joint height of 0.70 mm, a solder joint diameter of 0.85 mm, a substrate thickness of 0.51 mm, and a mold compound height of 1.12 mm. Implementing this optimized configuration led to a significant 4.07% reduction in average stress Δσ for the critical thin-layer elements within hazardous solder joints. Moreover, the extension of the thermal fatigue life was notably improved, achieving an impressive 51.72% increase.

Residual Stress Testing and Simulation Analysis of Crystal Structures of Electronic Device Materials

In this paper, we analyze the residual stress of different components of the crystal structures of electronic device materials following exposure to elevated temperatures using a combination of experimental tests and finite element simulations. X-ray diffraction (XRD) and LXRD micro-area residual stress analyzer were employed to determine the residual strain and stress of the CBGA sample encapsulation cover and solder joints. Subsequently, the experimental data were utilized to verify the accuracy of the simulation. The discrepancy between experimental measurements and simulation outcomes of the residual stress following reflow soldering of CBGA-assembled micro-solder joints is below 14%. The analysis also included thermal warping deformation of the CBGA encapsulation cover and how the residual stress was influenced by the diameter, spacing, and height of the solder joints. The study reveals that the residual stress following reflow soldering of BGA solder joints is non-uniformly distributed within the array. Within a single solder joint, residual stress gradually increases in distribution from its middle to the point where it make contact with the PCB and chip, with the highest level of residual stress observed where the solder joint contacts the chip. The variation in material parameters, such as the coefficient of thermal expansion, is the primary cause of thermal warping deformation on the surface of CBGA encapsulation covers. Three primary factors significantly impact the residual stress on BGA solder joints: solder joint diameter, spacing, and height. The maximum value is inversely proportional to the height of the solder joints and the residual stress. Conversely, the diameter and spacing of the joints are positively proportional to the highest value. When the diameter of the solder joint is increased from 0.55 mm to 0.75 mm, the maximum residual stress in the BGA solder joint increases from 37.243 MPa to 36.835 MPa. Conversely, increasing the height of the solder joint from 0.36 mm to 0.44 mm reduces the stress from 39.776 MPa to 36.835 MPa.

Structural optimization of thermal stresses in BGA solder joints based on improved BP neural network-genetic algorithm

Structural optimization of thermal stresses in BGA solder joints based on improved BP neural network-genetic algorithm

Stout hourglass – The ideal shape for robust solder joints

The optimum shape of solder joints in an electronic assembly that experienced differential thermal expansion between its constituting members was analysed using advanced beam analysis. The advanced beam analysis is capable of modeling the exact geometry of solder joints. The shearing and bending stresses in solder joints of multiple shapes: barrel, slender hourglass, and stout hourglass, were evaluated. The barrel-shape solder joints returned the highest magnitudes of shear stress, bending stress, and von mises stress. The slender-hourglass-shape solder joints that have superior in-plane shear compliance returned the lowest magnitude of shear stress at 10% that of the barrel-shape solder joints, and a von mises stress that is 27% that of the barrel-shape solder joints. The stout-hourglass-shape solder joints returned the lowest magnitude of bending stress at 13% that of the barrel-shape solder joints, and a von mises stress that is 14% that of the barrel-shape solder joints. The substantial reduction in the magnitude of von mises stress by the stout-hourglass-shape solder joints is estimated to give an eight-time improvement in the temperature cycling life of solder joints.

Failure Analysis of Printed Circuit Board Solder Joint under Thermal Shock

Investigating the failure mechanism of solder joints under different temperature conditions is significant to ensure the service life of a printed circuit board (PCB). In this research, the stress and strain distribution of a PCB solder joint was evaluated by high- and low-temperature thermal shock tests. The cross-section of the solder joint after thermal shock testing was measured using a 3D stereoscopic microscope and SEM equipped with EDS. The microstructure of the lead-free solder joint and the phase of the intermetallic compound (IMC) layer were studied by XRD. The working state of the PCB solder joint under thermal shock was simulated and analyzed by the finite element method. The results show that thermal shock has a great effect on the reliability of solder joints. The location of the actual crack is consistent with the maximum stress–strain concentration area of the simulated solder joint. The brittle Cu6Sn5 and Cu3Sn phases at the interface accelerate the failure of solder joints. Limiting the growth of Cu6Sn5 and Cu3Sn phases can improve the reliability of solder joints to a certain extent.

Numerical Analysis of 3D CSP MEMS Under Thermal Cycle-Impact Coupled Multiphysics Loads

In this paper, reliability analysis of 3D CSP MEMS and IC under thermal cycle-impact coupled multi-physics loads was investigated. COMSOL Multiphysics, a finite element software, was used to analyze our device’s mechanical behavior under a -55°C/125 °C thermal cycling and 1500G@1ms with half-sine pulse impact coupled load. In details, MEMS chip was bonded on a silicon interposer by solder balls and an application specific integrated circuit (ASIC). Thermal stress of single solder joint, whole device, and the simulation of device reliability under different magnitudes and forms of mechanical shock were carried out, respectively. Combining the effects of impact and thermal stress loads, we hope to find out the failure modes of interconnect structures for future design including solder joints and whole device. The stress distribution and deformation of the overall device will be carried out for layout optimization of interconnect structures.

Board-Level Drop Impact Reliability Analysis of Dual-Side Molding System-in- Package (SiP) Modules

System-in-package (SiP) modules are widely used in portable electronics such as Internet of Things (IoT) devices and mobile consumer equipment since they integrate multiple components in a single package and thus facilitate device miniaturization. An advanced packaging technology referred to as dual-side molding (DSM) has recently been proposed as a means of achieving even smaller form factors and lower cost solutions. However, shrinking the package size reduces the solder joint connection area between the SiP module and the printed circuit board (PCB). Consequently, the board-level drop reliability may be severely impaired. Accordingly, the present study utilizes a numerical model to investigate the board-level solder joint reliability of a DSM SiP package in drop impact tests performed in accordance with the Joint Electron Device Engineering Council (JEDEC) standard. The validity of the numerical model combined with a full-factorial design method is then employed to examine the effects of the main design parameters of the DSM SiP package on the reliability of the solder joints in the drop impact test. Overall, the present results show that a higher EMC coverage of the solder ball joints yields a significant improvement in the solder joint reliability. In addition, a larger solder joint volume is beneficial in reducing the solder joint stress by absorbing a greater proportion of the impact load and energy produced in the drop impact event.

Next-Generation High-Density PCB Development by Fan-Out RDL Technology

High-density interconnect (HDI) printed circuit boards (PCBs) are in high demand for smartphones, particularly those with fifth generation (5G) functionality, due to their smaller form factors, higher interconnection densities, and improved integrative ability. Various advanced PCB technologies are available, including HDI PCBs and substrate-like PCBs (SLPs). However, even for substrate-like PCBs, the line width (L) and spacing (S) of the copper traces are limited to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25~\mu \text{m} / 25~\mu \text{m}$ </tex-math></inline-formula> , and fine-line development also faces yield and cost challenges. Accordingly, the present study utilizes an redistribution layer (RDL) first fabrication process to develop a fine line width/spacing ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10~\mu \text{m} / 10~\mu \text{m}$ </tex-math></inline-formula> ) Fan-out interposer (FOI) on PCB architecture with a higher I/O (Input/Output) density, greater yield, and lower cost. A three-dimensional (3D) ANSYS finite element (FE) model combined with volume fractions approach applied to equivalent thermomechanical properties of the multilayer RDL is introduced. The validity of the simulation model is confirmed by comparing the numerical results for the out-of-plane deformation of the top surface of the FOI with the experimental observations. Then, the effects of five design parameters on the warpage and solder joint stress performance of the FOI-PCB architecture are identified through parametric analysis. Finally, a second-order response surface methodology (RSM) model and Box-Wilson central composite design (CCD) method are employed to examine the interactive effects of the structural design factors of the FOI-PCB architecture on the FOI warpage under typical manufacturing thermal loading conditions. It is shown that a smaller overall size of the FOI is beneficial in reducing the warpage by minimizing the coefficient of temperature expansion (CTE) mismatch between the interposer and the PCB.

Machine learning for board-level drop response of BGA packaging structure

Board-level drop responses are critical to evaluate the mechanical reliability of solder joints to serve as electrical and mechanical connections in electronic devices to resist failure due to drop impact. A machine learning (ML) model based on the back propagation (BP) method is proposed for predicting three-dimensional board-level drop responses of the ball grid array (BGA) packaging structures. Compared with conventional finite element (FE) simulations with solid elements, the proposed approach with a deep neural network is more than three orders of magnitude faster in terms of computational efficiency. More importantly, detailed stress and strain of all solder joints and also the warpage of the printed circuit board (PCB) can be accurately predicted throughout the drop process. According to the contact type between BGA packaging structure and rigid ground, the drop conditions are divided into three types: surface contact, line contact and point contact. After training the ML model, the obtained nonlinear mapping relation can well predict the mechanical response of solder joints in BGA packaging structures. To significantly extend the application scope, the trained ML model could reasonably predict the dynamic responses of BGA structures with the drop angles which are beyond the training samples. Compared with FE results, the prediction accuracy of the proposed ML model is objectively measured by the Pearson correlation coefficient which is found to be above 0.95 after estimating the stress, strain and energy density of solder joints and PCB warpage. Except for those stress, train and energy density values close to 0, the prediction errors are mostly less than 10% compared with the finite element simulation values. Therefore, it is affirmed that the computational efficiency and accuracy of the proposed ML method are satisfactory to replace the traditional time-consuming FE modeling for predicting the dynamic responses of board-level BGA packaging structures even under more extreme and complicated loading conditions.

Research on the reliability of Micro LED high-density solder joints under thermal cycling conditions

For the purpose of studying the effect of high-density, small-size solder joints on the thermal fatigue life of display devices, a 3D model of the corresponding device structure is established, using finite element analysis methods, and using Anand constitutive equations and Coffin-Manson life prediction models. The equivalent stress and strain change law of an indium solder joint with a diameter of 10 μm under thermal cycling loading conditions is explored, and the key position of the solder joint damage is inferred based on the simulated strain cloud diagram. In addition, the influence of different bump height, bump contact area and Under-Bump Metallization (UBM) thickness on the thermal fatigue life of solder joints is studied separately. The final simulation results show that the location where the solder joint may be damaged first is at the point on the outer side where the solder joint is connected to the UBM on the edge away from the center point. The height of the bump and the contact area of the bump have a significant effect on its thermal fatigue life. In the actual experiment, we should focus on the impact of this aspect.

Finite Element and Experimental Analysis of Spacer Designs for Reducing the Thermomechanical Stress in Double-Sided Cooling Power Modules

This article addresses the role of metal spacer design in reducing the thermomechanical stress of solder joint in automotive double-sided cooling power electronics modules. The performance and reliability of power modules are becoming increasingly important in electrified vehicles. A double-sided cooling structure has dual heat sinks placed on the top and bottom of the module and is the most promising solution for improving the thermal reliability of power modules. One of the unique components of this structure is its metal spacers, which are responsible for both electrical and thermal conductions via the connecting embedded power semiconductor dies and their top-side substrates. Reported spacers are typically cuboid in shape, providing a relatively large solder-contact area with the power dies. This large contact area is beneficial in reducing the electrical and thermal resistances, but it increases thermomechanical stress and may accelerate the deterioration of die-bonded solders. This article explores the role of three new spacer shapes in reducing the thermomechanical stress of the solder. Their performances are validated using both the finite-element method (FEM) simulations and thermal cycling experiments. In this article, an octagon-surface spacer demonstrates the best solder reliability compared to the two other designs and the conventional cuboid spacer.

Numerical and experimental study on laser soldering process of SnAgCu lead-free solder

Laser soldering has been widely used in the connection of the electronic components and printed circuit boards. Normally, the temperature and thermal stress of solder joints significantly influence the soldering performance and the reliability of solder joints. However, it is difficult to be accurately measured by the experiment during laser soldering process. In order to reveal the effect of laser process parameters on the temperature and thermal stress of SnAgCu solder joints, a novel 3D transient thermo-mechanical coupling numerical model is proposed using finite element method. The numerical simulation results reveal that the temperature and the thermal stress as well as the deformation of the as-soldered samples are proportional to laser output power and output time. These results demonstrate that the fine and uniform microstructure is obtained for SnAgCu solder and the micro Vickers hardness reaches to the maximum value of 38.3 N at the condition of laser output power of 16 W and laser output time of 0.8 s. The good consistency between the experimental and simulation results proves that the finite element model may effectively predict the temperature distribution and stress distribution, which provides a new pathway for the optimization of the laser soldering parameters in the application of electronic components and PCB.

Research on solder joint stress damage evaluation method based on discrete SSI model

Based on the discrete SSI(Stress-strength-interference) model, this paper establishes a stress damage evaluation method for the through-hole insertion process. First, based on the Monte Carlo sampling method, the mean value of solder joint stress was clarified, and a stress-strength interference model for through-hole insertion was established. Secondly, after calculating the shape of the solder joints of the through-holes, the simulated load input curve is determined and the stress simulation is performed to obtain the stress and strain simulation results. The stress and strain of the PCB board are measured through experiments. Finally, a random stress model of solder joints was established by Monte Carlo sampling, and a constant strength model of through-hole solder joints was established in combination with material strength. According to the stress strength interference model, the failure probability of process stress damage was calculated, and the stress damage evaluation of solder joints in through-hole insertion process was realized.

Thermal performance and fatigue life prediction of POP stacked chip assembly under thermal cycling load

PurposeThis paper aims to perform experimental test on fatigue characteristics of package on package (POP) stacked chip assembly under thermal cycling load. Some suggestions for design to prolong fatigue life of POP stacked chip assembly are provided.Design/methodology/approachThe POP stacked chip assembly which contains different package structure mode and chip position was manufactured. The fatigue characteristics of POP stacked chip assembly under thermal cycling load were tested. The fatigue load spectrum of POP stacked chip assembly under thermal cycling load was given. The fatigue life of chips can be estimated by using the creep–fatigue life prediction model based on different stress conditions.FindingsThe solder joint stress of top package is significantly less than that of bottom solder joints, and the maximum value occurs in the middle part of the solder joints inner ring.Originality/valueThis paper fulfils useful information about the thermal reliability of POP stacked chip assembly with different structure characteristics and materials parameters.

Structural and mechanical analyses of soldering materials containing Pb, Sn, Ag, Cu, Bi and Zn

In present work the microstructural and mechanical properties (such as shear stress, shear strain, deformation and creep behaviour) of solder joints of four different solders at temperatures of 100 °C and 150 °C was studied. The soldering materials included in this study were: Type A—Sn-36.00Pb-2.00Ag, Type B—Sn-3.80Ag-0.70Cu, Type C—Sn-3.30Ag-3.82Bi and Type D—Sn-8.00Zn-3.00Bi. Microstructure and mechanical properties of solders were studied by using Scanning Electron Microscopy (SEM), Energy Dispersive Spectroscopy (EDS) and Universal Testing Machine. It has been observed that the mechanical properties of Type B are not significantly changed with increase in temperature as compared to other materials.

Evaluation of the relationship between stress and lifetime of Pb-free solder joints subjected to vibration load using a generalized local stress approach

The article proposes a generalized high cycle fatigue evaluation methodology for solder joints based on a local stress finite element method (FEM) and compares with experimental results. A method to predict the damage initiation of surface mount technology (SMT) solder joints is accomplished in this article by making use of generic coupon level SAC387 solder specimens. High cycle fatigue (HCF) experiments conducted on generic solder specimens are followed by means of FKM guidelines, which are translated to microelectronic elements for the first time. The FEM predicted lifetime values of solder joints agree with the experimental results performed on SMT components. In addition, the overall results show that the predicted values act as a threshold damage line from which the solder joint failure regimes can be differentiated. The results also show the differences in the predicted damage line and failure line for SMT solder joints.