Stress-induced Voiding Failures Research Articles

Role of W and Mn for reliable 1X nanometer-node ultra-large-scale integration Cu interconnects proved by atom probe tomography

We used atom probe tomography (APT) to study the use of a Cu(Mn) as a seed layer of Cu, and a Co(W) single-layer as reliable Cu diffusion barriers for future interconnects in ultra-large-scale integration. The use of Co(W) layer enhances adhesion of Cu to prevent electromigration and stress-induced voiding failures. The use of Cu(Mn) as seed layer may enhance the diffusion barrier performance of Co(W) by stuffing the Cu diffusion pass with Mn. APT was used to visualize the distribution of W and Mn in three dimensions with sub-nanometer resolution. W was found to segregate at the grain boundaries of Co, which prevents diffusion of Cu via the grain boundaries. Mn was found to diffuse from the Cu(Mn) layer to Co(W) layer and selectively segregate at the Co(W) grain boundaries with W, reinforcing the barrier properties of Co(W) layer. Hence, a Co(W) barrier coupled with a Cu(Mn) seed layer can form a sufficient diffusion barrier with film that is less than 2.0-nm-thick. The diffusion barrier behavior was preserved following a 1-h annealing at 400 °C. The underlayer of the Cu interconnects requires a large adhesion strength with the Cu, as well as low electrical resistivity. The use of Co(W) has previously been shown to satisfy these requirements, and addition of Mn is not expected to deteriorate these properties.

Prediction of Stress Induced Voiding Reliability in Cu Damascene Interconnect by Computer Aided Vacancy Migration Analysis

The method of computer aided vacancy migration analysis has been developed to predict the stress induced voiding (SiV) reliability. In this method, distribution of hydrostatic stress was calculated by the finite element analysis (FEA), and vacancy concentration distribution was calculated by the finite difference analysis (FDA). In this paper, SiV acceleration tests were conducted in various widths of Cu lines in organic ultralow-k dielectric (Cu/Ta/ULK/SiCN) or silicon oxide dielectric (Cu/Ta/SiO2/SiCN) and these results were compared with the results of the vacancy migration analyses. The number of SiV failures increased in the line with width of 0.35 µm for Cu/Ta/SiO2/SiCN interconnects and 0.20 µm for Cu/Ta/ULK/SiCN interconnects, respectively, under SiV acceleration tests. The results obtained by vacancy migration analysis show similar behavior as the results of SiV acceleration tests. These results reveal that the vacancy migration analysis is useful to predict reliability of interconnects.

Effects of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voiding (SIV) in Cu Dual-Damascene Interconnects

Stress-induced voiding (SIV) is a serious problem in Cu dual-damascene interconnects (DDIs). The stress gradient under vias is the driving force of vacancy diffusion and void generation, therefore stress control in Cu-DDI is an important factor for suppressing SIV. In this study, the stress effect of upper Cu film on SIV in lower Cu lines is investigated, and the stress distribution in Cu-DDI is analyzed by finite element analysis. It is found that SIV in the lower Cu lines is strongly affected not only by the width of lower lines but also by the metallurgical properties of the Cu film in upper metals. Suppression of tensile stress in the via of the upper Cu film decreases the stress gradient in the lower line around the via, and eventually, the driving force of vacancy diffusion to the via bottom. Control of the metallurgical properties to suppress Cu creep during annealing is a key factor for decreasing SIV in lower Cu lines. High-temperature deposition of Cu film with a small coefficient of thermal expansion (CTE) is a solution to suppressing SIV failure in Cu-DDIs.