Stress-induced Leakage Current Research Articles

Performance Comparison of SONOS-Type UV TD Sensor Using Indium Tin Oxide-Aluminum Oxide-Zirconia Aluminum Oxide-Silicon Oxide-Silicon and Indium Tin Oxide-Aluminum Oxide-Hafnium Aluminum Oxide-Silicon Oxide-Silicon

This study compares the performance of two types of capacitive devices, indium tin oxide-aluminum oxide-zirconia aluminum oxide-silicon oxide-silicon (IAZAOS) and indium tin oxide-aluminum oxide-hafnium aluminum oxide-silicon oxide-silicon (IAHAOS), as silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory (NVM) total dose of ultraviolet radiation (UV TD) sensors. Results show that IAZAOS with zirconia aluminum oxide as the charge-trapping layer outperforms IAHAOS with hafnium aluminum oxide for a UV TD sensor. After exposure to UV TD irradiation of 100 mW·s/cm2, the threshold voltage (VT) change of IAZAOS is almost 1.25 times that of IAHAOS. The study also found that annealing can significantly improve the response performance of IAZAOS UV TD sensors. Furthermore, IAZAOS devices with partially smaller nanocrystals in the charge-trapping layer greatly enhance the response of SONOS-type UV TD sensors. The study also compared the constant voltage stress-induced leakage current (CVSILC) and found that the CVSILC for annealed IAZAOS devices is 1000 times smaller than that of IAHAOS devices. Moreover, the IAZAOS-I2Z2 exhibits a superior performance regarding irradiation/refresh cycle endurance as compared to the IAHAOS-I2H1 device. These findings suggest that IAZAOS capacitive devices have superior performance and potential for use in SONOS-type UV TD sensors.

An Investigation of SILC Degradation under Constant Voltage Stress in PDSOI Devices.

The stress-induced leakage current (SILC) degradation of partially depleted silicon in insulator (PDSOI) devices under constant voltage stress (CVS) was studied. Firstly, the behaviors of threshold voltage degradation and SILC degradation of H-gate PDSOI devices under constant voltage stress were studied. It was found that both the threshold voltage degradation and SILC degradation of the device are power functions of the stress time, and the linear behavior between SILC degradation and threshold voltage degradation is good. Secondly, the soft breakdown characteristics of the PDSOI devices were studied under CVS. Thirdly, the effects of different gate stresses and different channel lengths on the threshold voltage degradation and SILC degradation of the device were studied. The results showed SILC degradation of the device under positive CVS and SILC degradation of the device under negative CVS. The shorter the channel length of the device was, the greater the SILC degradation of the device was. Finally, the influence of the floating effect on the SILC degradation of the PDSOI devices was studied, and the experimental results showed that the degree of SILC degradation of the floating device was greater than that of the H-type grid body contact PDSOI device. This showed that the floating body effect can exacerbate the SILC degradation of PDSOI devices.

Oxygen vacancy contributions to the electrical stress response and endurance of ferroelectric hafnium zirconium oxide thin films

Despite its scalability and CMOS process compatibility, the limited endurance and sub-optimal stress response of ferroelectric Zr-substituted hafnia [(Hf,Zr)O2] have been one of the key impediments toward its integration into practical device and technology applications. Here, using electrical measurements complemented by photoluminescence spectroscopy, we investigate the underlying mechanisms behind this behavior in 10 nm thick W/Hf0.5Zr0.5O2/W capacitors. Analyzing the evolution of leakage current with stress cycles and the spectroscopic response of the stress-induced leakage current, we attribute the behavior to defect levels, which lie at 0.6 eV from the conduction band edge of the ferroelectric. Photoluminescence spectroscopy, in turn, further corroborates the defect level's position within the bandgap while enabling its attribution to the presence of oxygen vacancies. This work helps to identify oxygen vacancies as the key factor responsible for the degraded endurance and stress response in (Hf,Zr)O2 and subsequently motivates the exploration of methods to reduce the oxygen vacancy concentrations without destabilizing the ferroelectric orthorhombic phase.

Breakdown-limited endurance in HZO FeFETs: Mechanism and improvement under bipolar stress

Breakdown is one of main failure mechanisms that limit write endurance of ferroelectric devices using hafnium oxide-based ferroelectric materials. In this study, we investigate the gate current and breakdown characteristics of Hf0.5Zr0.5O2/Si ferroelectric field-effect transistors (FeFETs) by using carrier separation measurements to analyze electron and hole leakage currents during time-dependent dielectric breakdown (TDDB) tests. Rapidly increasing substrate hole currents and stress-induced leakage current (SILC)-like electron currents can be observed before the breakdown of the ferroelectric gate insulator of FeFETs. This apparent degradation under voltage stress is recovered and the time-to-breakdown is significantly improved by interrupting the TDDB test with gate voltage pulses with the opposite polarity, suggesting that defect redistribution, rather than defect generation, is responsible for the trigger of hard breakdown.

Evidence of Charging and Storage at the MoS2/Si Interface

Non-volatile memory chips are important in devices for data storage, where demand kept increasing and the demand of large capacity of storage grew with the development in technology. Flash memory is one of the non-volatile memory devices that has a simple structure that is based on CMOS basic structure. Flash memory was introduced by Toshiba in 1984, which is an electrically erasable/programable non-volatile memory device [1]. Due to the development new technology the demand for size scale down of the memory structure was high, at which the size was kept on being reduced. At sizes less than 65nm flash memory started to show different problem including charge loss and the stress-induced leakage current, due to the tunnelling oxide thickness reduction. [2,3]. The structure of the flash memory has been developed to overcome the issues due to size reduction by introducing nanoparticles to the floating gate, which showed huge development. This development made researchers explore different nanoparticles including 2D materials. 2D materials has distinctive electrical, optical, chemical, and mechanical properties that makes them interesting to be implemented in new technology [4]. One of the interesting 2D materials is Molybdenum disulfide (MoS2). MoS2 have a multitude of features such as high strength, flexibility and has better quantum yield than bulk MoS2 [5]. 2D films of MoS2 can be widely used in various devices for their electronic, optical, and catalytic properties [6]. In this work MoS2 nanoflakes were bonded to silicon to study the charge transport at the interface.The initial bulk MoS2 was in crystal form, which was used to prepare the MoS2 nanoflakes. The preparation procedure for the MoS2 flakes was by using mechanical exfoliation technique. Nitto SPV224 PVC tape had been used to exfoliate bulk MoS2, where part of the bulk MoS2 crystal is placed on the sticky part of the tape. The tape is then folded on the MoS2 piece with the tape surrounding the crystal on the top and bottom. The tape is then separated from each other, which results in exfoliation of the MoS2 into flakes. The more the steps are repeated of this process, the thinner the flakes are. The flakes on the tape were transferred to a p-Si wafer on a hot plate at 50C and bonded to create the MoS2/Si interface.The achieved MoS2 nanoflakes on p-Si wafer sample had been imaged using AFM topography and conductivity measurements. The AFM images were collected to identify the distribution of the flakes. AFM images showed clear flakes on the p-Si wafer at which they were distributed randomly over the surface. The thickness of single monolayer flakes measured was 0.65nm and two monolayer flakes were 1.3 nm. Furthermore, conductive AFM was employed to obtain the IV curve over the flake and obtain their electrical properties, where forward and reverses scanning was done showing a hysteresis loop. The hysteresis observed showed a voltage window gap of around ∆Vth=0.5 V. This indicates electron tunneling and charge storage at the MoS2/Si interface or in the MoS2. Finally, the results, highlight the potential use of 2D MoS2 flakes in future no power memory devices.

Characteristics of Nickel Oxide Modified Zr-Doped HfO2 High-k Thin Films

The high-k thin film can be used to replace SiO2 as the gate dielectric in nano MOS devices to improve the performance and reliability (1,2,3). The HfO2 high-k dielectric suffers from the low crystallization temperature, e.g., <600˚C (4,5). The Zr-doped HfO2 (ZrHfO) dielectric has a higher crystallization temperature and better properties than the undoped HfO2 film based on the same EOT (6-9). The sub 1 nm EOT ZrHfO gate dielectric has been demonstrated (6,10). There are reports that high-k dielectric properties could be improved by dispersing metal particles into the structure (11,12). In this work, the authors investigated changes of material and electrical properties of the ZrHfO gate dielectric by embedding nickel oxide (NiO) into the structure.The ZrHfO/NiO/ZrHfO dielectric stack was sputter deposited on a HF pre-cleaned p-type Si (100) wafer in one-pump down. The bottom and top ZrHfO films were deposited from a Hf/Zr target in Ar/O2 at 5 mTorr for 2 min and 10 min, separately. The NiO film was sputter deposited from a Ni target in Ar/O2 at 5 mTorr for 20s. The PDA was done at 800°C under N2 for 60 sec. The nanocrystalline NiO (nc-NiO) was formed in the dielectric layer, as shown in Figure 1. The gate electrode and backside ohmic contact were formed from the sputter deposited Al. The control sample, i.e., ZrHfO gate dielectric without the embedded NiO, was also prepared for comparison.Figure 2 shows C-V hysteresis curves of the control and nc-NiO embedded samples. All samples show counter-clockwise hysteresis. The control sample has a larger hysteresis than the nc-NO embedded sample has, i.e., 0.2V vs. < 0.02V. The large number of trapped charges in the control sample reflects the incomplete passivation of defects in the PDA step (13,14). The small amount of nc-NiO effectively reduced the oxygen deficiencies or vacancies in the film (13,15). The EOTs of the control and nc-NiO embedded samples are 8 nm and 7.7 nm, respectively. The embedded nc-NiO increase of bulk film’s permittivity due to its dipole moment (16). Similar phenomenon was observed in other nanoparticles embedded high-k stack (11,13).The stress-induced leakage current (SILC) of the capacitor was investigated. The leakage current was measured after stress with a negative gate voltage (-Vg ) for various periods. The leakage current increases with the increase of the stress time, which is attributed to the deterioration of the film (17,18). The nc-NiO embedded sample has a large leakage current than the control sample due to its conductive nature (19).More detailed results on the influence of nc-NiO on the breakdown mechanism using the ramp-relax method will be reported (20).This study was partially sponsored by NSF Grant 0926379. C.-H. Yang thanks Professor Way Kuo of City University of Hong Kong for his advice and support throughout this study. The International Technology Roadmap for Semiconductors. Semiconductor Industry Association, December (2003).C. Hu, Nanotech., 10, 113 (1999).J. J. Lee, X. Wang, W. Bai, N. Lu and D.-L. Kwong, IEEE Trans. Elec. Dev., 50, 2067 (2003).J. Robertson, J. Vac. Sci. Technol. B, 18, 1785 (2000).J. Lu, Y. Kuo, J. Yan and C.-H. Lin, Jpn. J. Appl. Phys., 45, L 901 (2006).Y. Kuo, J. Lu, S. Chatterjee, J. Yan, T. Yuan, H.-C. Kim, W. Luo, J. Peterson and M. Gardner, ECS. Trans., 1, 447 (2006).D. Triyoso, ECS Trans., 3, 463 (2006).Y. Kuo, ECS Trans., 3, 253 (2006).Y. Kuo, ECS Trans., 2, 13 (2006).J. Yan, Y. Kuo, and J. Lu, ECS Solid-State Lett., 10, H199 (2007).R. Ravindran, K. Gangopadhyay, S. Gangopadhyay, N. Mehta, and N. Biswas, Appl. Phys. Lett., 89, 263511 (2006).G. C. Vezzoli, M. F. Chen, and J. Caslavsky, Ceram. Int., 23, 105 (1997).C.-H. Lin and Y. Kuo, J. Electrochem. Soc., 158, G162 (2011).N. Zhan, M. C. Poon, C. W. Kok, K. L. Ng, and H. Wong, J. Electrochem. Soc., 150, F200 (2003).H. Sim, H. Chang, and H. Hwang, Jpn. J. Appl. Phys. Part 1, 42, 1596 (2003).S. C. Chung, S. Krüger, G. Pacchioni, and N. Rösch, J. Chem. Phys., 102, 3695 (1995).S. Chatterjee, Y. Kuo, J. Lu, J.-Y. Tewg, and P. Majhi, Microelec. Rel., 46, 69 (2006).S. Chatterjee, Y. Kuo, J. Lu, Microelec. Eng., 85, 202 (2008).J. Feinleib and D. Adler, Phys. Rev. Lett., 21(14), 1010 (1968).W. Luo, Y. Kuo and W. Kuo, IEEE Trans. Dev. Mat. Rel., 4, 488 (2004). Figure 1

Electrically detected magnetic resonance and near-zero field magnetoresistance in 28Si/28SiO2

We report on electrically detected magnetic resonance (EDMR) and near-zero-field magnetoresistance (NZFMR) measurements observed through spin-dependent trap-assisted-tunneling on unpassivated Si/SiO2 metal–insulator–semiconductor capacitors comparing those containing silicon of natural isotopic abundance and silicon depleted of 29Si. Although our measurements involve monitoring the spin-dependence of the trap-assisted-tunneling current responsible for leakage across the oxide, the EDMR spectra resemble that of a combination of Pb0 and Pb1 silicon dangling bonds sites at the Si/SiO2 interface. Additionally, we observe a substantial narrowing of the NZFMR response with the removal of 29Si nuclei. The breadth of the NZFMR response is strongly influenced by hyperfine interactions. Since superhyerfine interactions between 29Si nuclei and silicon dangling bonds at the Si/SiO2 interface are a full order of magnitude stronger than such interactions involving silicon dangling bonds defects (E′ centers) within the oxide, the NZFMR results also strongly suggest a response dominated by Si/SiO2 interface trap defects. These results collectively suggest very strongly that the leakage currents that we observe involve tunneling from Si/SiO2 Pb dangling bonds to defects within the oxide. Our results thus offer fundamental insight into technologically important phenomena involving oxide leakage currents in metal–oxide–semiconductor devices such as stress induced leakage currents and time dependent dielectric breakdown.

A Stochastic Framework for the Time Kinetics of Interface and Bulk Oxide Traps for BTI, SILC, and TDDB in MOSFETs

A stochastic reaction–diffusion drift model is used to simulate the time kinetics of interface and bulk oxide traps responsible for bias temperature instability (BTI), stress-induced leakage current (SILC), and time-dependent dielectric breakdown (TDDB) in MOSFETs. Trap generation and passivation are calculated using dissociation and repassivation of trap precursors and simultaneous diffusion and/or drift of atomic, molecular, and/or ionic species. The average of multiple stochastic simulations is used to qualitatively explain the measured BTI and SILC data. The difference in BTI and SILC time kinetics, variation in SILC time kinetics across reports, and oxide thickness dependence of TDDB Weibull slope variation are also qualitatively explained.

Reliability Characteristics of Diamond-Like Carbon as Gate Insulator for Metal–Insulator–Semiconductor Application

This study presents the reliability of diamond-like carbon (DLC) ultrathin films fabricated by DC magnetron sputtering as the gate dielectric layer in metal–insulator–semiconductor (MIS) devices. Stress-induced leakage current (SILC) and time-dependent dielectric breakdown (TDDB) measurements were performed to determine the reliability of the devices. The MIS device with DLC film deposited at 1100-V bias exhibited little variation of SILC under different constant voltage stress times and had a long TDDB lifetime. The results indicate excellent reliability of DLC films used as gate dielectrics. Moreover, several soft breakdown events occurred during TDDB measuring. An extended percolation model was adopted for explanation of the current versus time characteristics.

Impact of Electrical Stress on Defect Generation in Thin GeO2/Ge Gate Stacks Fabricated by Thermal Oxidation

The impact of electrical stress on the defect generation behaviors in thin GeO2/n-Ge gate stacks has been investigated through the measurement of the time-dependent dielectric breakdown (TDDB) and the stress-induced leakage current (SILC) characteristics. A multiple-spot breakdown (BD) event is confirmed, as well as a larger SILC generation probability compared with that in SiO2/Si structures. It is found that the slow trap generation is dominant by the amount of injected electron fluence ( ${Q} _{{\text {inj}}}$ ), and the fix charge generation is attributed to both ${Q} _{{\text {inj}}}$ and GeO2 thickness.

(Invited) Multiscale Modeling of Atom Scale Defects for Electronic Devices Engineering

We present in this paper a multiscale modeling platform that is used to study the effect of atomic level defects on the electrical characteristics of nanoscale devices. This allows identifying ways to engineer material (and defects) and device properties to achieve optimum performance and reliability in logic and memory circuits.Atom scale defects in multilayer thin film material stacks have a profound effect on the electrical performance and reliability of nanoscale electronic devices. These defects include both point defects such as vacancies and interstitial ions as well as extended defects such as grain boundaries, dislocations.We developed a multiscale modeling platform connecting the atomic material properties to the electrical device performance, which allows understanding the optimum material characteristics for different types of logic devices and memory cells. These include logic devices, conventional memories (e.g. DRAM, 3D-NAND) as well as emerging devices (e.g. RRAM, PCM). The simulations allow learning how to scale these technologies through material and process improvement and how to co-optimize materials and devices. I. MULTISCALE MODELING Figure 1 shows the flowchart of the multiscale multiphysics simulation platform along with its main blocks [1]. The ab-initio material properties relevant for the electrical device performances (e.g. bandgap, permittivity, defects energies, defect diffusion barrier ...) are computed using DFT calculations (gray portion). These material properties are then used for the device level simulations (green portion), and the output device electrical characteristics allows calibrating the circuit simulations (yellow portion). The device simulator couples classical and quantum charge transport mechanisms with stress induced material changes (e.g. atomic breakage, creation and diffusion of ions/vacancies), whose occurrence probability is calculated by accounting for the temperature increase and power dissipation associated with the current.The charge transport mechanisms include drift/diffusion in conduction band (CB) or valence band (VB), which is the primary carrier transport mode in semiconductors, and Trap Assisted Tunneling (TAT), which is the dominant mechanism in dielectrics and amorphous semiconductors. Defects with energy levels in the bandgap play a crucial role in the conduction, assisting electron transfer. The charge transport is coupled to the kinetics of atomic level material modifications caused by electrical and thermal stresses encompassing distortion and breakage of bonds, diffusion of vacancies and interstitial ions leading to changes in local fields, stoichiometry and phase changes including ferroelectricity. This allows modeling the reliability of devices to be calculated in addition to static electrical characteristics as well as the device variability.In this presentation, we will show how this multiscale simulation platform can be used to extract defect properties for advanced logic stack as well as to understand the physics of operation of RRAM devices. II. UNDERSTANDING DEFECT IMPACT ON LOGIC STACKS The multiscale approach presented in Section II can be used to characterize and understand the role of the dielectric defects on device electrical characteristics and reliability. Oxide defects are at the bases of the most relevant reliability phenomena in both logic and memory devices, e.g. Random Telegraph Noise (RTN), Bias Temperature Instabilities (BTI), Stress Induced Leakage Currents (SILC) and breakdown (BD). Identifying their nature and their spatial/energy distributions in the dielectric stack is crucial for process optimization and device operation/reliability improvement. The developed simulation framework implements a fast defect spectroscopy (DS) technique based on the modeling and simulation of the charge transport within the dielectric. This technique is applied to identify the defects responsible for I-V, CV. GV in a variety of different stack configurations. III. UNDERSTANDING RRAM OPERATIONS We used this modeling platform proposed to investigate the kinetics of the operation processes of HfO2-based RRAM devices. Forming, set and reset operations are consistently described within the modeling framework described in Section II, accounting for species (i.e. O ions and vacancies) generation, recombination and diffusion.Simulations can reproduce the evolution of the current simulated for a full cycle comprised by forming, reset and set operations. The simulated current exhibits the expected features: an abrupt jump at forming, a gradual reduction in reset, and a lower set voltage compared to forming. The evolution of potential, temperature and generated oxygen vacancies and ions during simulations can be monitored to gain insights on the mechanisms controlling device operations, including the structural changes such as the creation and disruption of the conductive filament, as well as the high temperature reached during forming. IV. REFERENCES [1] GINESTRATM , http://www.mdlsoft.com Fig 1: Schematic flow chart describing the main blocks of multiscale simulation platform. Figure 1

Impacts of extra charges on trap level modulations at cSi/aSiO2 interface: correlations to leakage current recovery in oxide dielectric

Reliability issues in metal-oxide-semiconductor field-effect transistor (MOSFET) are closely related to oxide dielectric degradation under electric field stressing, such as stress-induced leakage current (SILC). Some studies show that SILC induced dielectric degradation can be cured by high-temperature annealing while some others show contradictory results. A possible microscopic mechanism could be related to different states of oxygen vacancies in the oxide dielectric because these defects contribute to the leakage current via trap-assisted tunneling (TAT). Here, by first-principles calculations, we demonstrate that the leakage current recovery can be explained in terms of the modulation of trap levels by extra charges. It is found that, with extra holes around the defect, the trap level will be moved far away from the Si valence band and leave the TAT window, which accordingly assists SILC recovery. On the contrary, with extra electrons around the defect, the trap level will be closer to the Si conduction band, having no contribution to the SILC recovery. This study provides a theoretical perspective on the dielectric recovery mechanisms by including the impacts of extra charges.

Buffer Vertical Leakage Mechanism and Reliability of 200-mm GaN-on-SOI

A comprehensive study on buffer vertical leakage mechanism and buffer reliability of 200-mm GaN-on-SOI is conducted in this paper. The buffer vertical leakage current versus bias is found to sequentially comprise three ranges of low-field leakage, variable-range hopping, and breakdown. The low-field leakage increase at high temperatures has been proven to be dominated by surface leakage. The stressing voltages of buffer time-dependent breakdown (TDB) measurements have a significant impact on shape factor $\beta $ . Stress-induced leakage current is observed in the wear-out phase of the TDB curves. Stress-and-sense measurements in this phase indicate that defects are generated probably around the threading dislocations, where more localized Joule heating and more defects are created by a positive feedback, and finally, the buffer breaks down due to thermal runway. At last, based on the Weibull plot and E-model, the operating voltage is extrapolated to be 470 V corresponding to an expected lifetime of 10 years at 175 °C, with area scaling to the drain terminal of a 150-mm power transistor and failures scaling to 0.01%. The qualification of GaN-on-SOI is crucial for future 200-V GaN power integrated circuit on this platform.

Lack of correlation between C-V hysteresis and capacitance frequency dispersion in accumulation of metal gate/high-k/n-InGaAs metal-oxide-semiconductor stacks

The correlation between capacitance-voltage hysteresis and accumulation capacitance frequency dispersion of metal gate/high-k/n-InGaAs metal-oxide-semiconductor stacks is experimentally assessed. Samples fabricated employing forming gas annealing (FGA) or substrate air exposure to obtain different densities of defects were thoroughly characterized and the results were compared with previous literature on the topic. Results indicate a lack of correlation between capacitance-voltage hysteresis and accumulation capacitance dispersion with frequency, suggesting that defects with remarkably different kinetics are involved in each phenomenon. This is assessed through the dependence of the capacitance-voltage hysteresis with DC bias and stress time, observing that permanent interface defect depassivation under bias has no effect on the hysteresis width after stress. Overall, capacitance-voltage hysteresis probes slow trapping mechanisms throughout the oxide and the bandgap, which are consistent with the negative charge trapping characteristic of the current-time curves for FGA samples at constant voltage stress. Instead, accumulation capacitance frequency dispersion probes defects with short trapping/detrapping characteristic times that can be linked to the stress induced leakage current of air exposed samples under constant DC stress. Experimental results indicate that each effect must be assessed separately due to the large difference in the kinetics of the probed defects.

Analysis of NBTI Degradation in nMOS-Capacitors and nMOSFETs

This paper presents a new attempt to further understand negative bias temperature instability (NBTI) stress in semiconductor devices. NBTI impact has been experimentally investigated on both p-substrate MOS (nMOS-capacitor) and nMOS transistors under accumulation condition, and new findings have been revealed. Indeed, nMOS-capacitor’s flat band shift ( $\boldsymbol {\Delta }\text{V}_{\mathbf {FB}}$ ) under NBTI stress has disclosed that time exponent ( ${n}$ ) and activation energy ( ${\mathbf{E}}_{\mathbf{a}}$ ) do vary with applied voltage stress pointing out to the contribution of two components, interface ( $\text{N}_{\mathbf {IT}}$ ) and oxide ( $\text{N}_{\mathbf {OT}}$ ) traps. Besides, the threshold electric field delimiting NBTI and stress induced leakage current can be well established. These findings have been confirmed by the appearance of a turn-around effect in nMOS transistors under NBTI stress. Moreover, charge pumping characterization has unveiled that NBTI degradation in nMOS transistor goes through two stages. First, only $\text{N}_{\mathbf {IT}}$ is created, then simultaneous generation of $\text{N}_{\mathbf {IT}}$ and $\text{N}_{\mathbf {OT}}$ takes part.

Effects of thermal and electrical stress on defect generation in InAs metal–oxide–semiconductor capacitor

Defects in HfO2 dielectric film caused by indium and arsenide diffusion from InAs were investigated. To investigate the dissociation of InAs during post-deposition annealing (PDA) at 600 °C, we analyzed the ratio of the elements on the surface of the oxide layer and the chemical states by using time-of-flight secondary-ion mass spectroscopy and X-ray photoelectron spectroscopy, respectively. In–As bonding was dissociated and In and As atoms were diffused through the HfO2 layer from InAs. Fortunately, the diffusion and trap density could be controlled by using a 1-nm-thick Al2O3 passivation layer.In addition, we used the nitridation process to control the trap density. We evaluated the thermal and electrical stability of three samples—HfO2/InAs, HfO2/Al2O3/InAs, and nitrided HfO2/Al2O3/InAs—by analyzing the change in trap density before and after PDA at 600 °C and the stress-induced leakage current. In conclusion, the passivation layer effectively improved the thermal and electrical stability, whereas the nitridation process using NH3 gas did not. Moreover, although nitridation could reduce the interfacial defect states, due to structure distortion, it induced the degradation of the device.

Understanding PBTI in Replacement Metal Gate Ge n-Channel FETs With Ultrathin Al2O3 and GeO&lt;italic&gt;x&lt;/italic&gt; ILs Using Ultrafast Charge Trap–Detrap Techniques

We report positive bias temperature instability data in replacement metal gate Ge n-channel metal–oxide–semiconductor field-effect transistors with an in-situ gate stack employing an ultrathin (5 A), stable Al2O3 interlayer (IL) using ultrafast (~microseconds) characterization techniques that ensure recovery artifact-free measurements. Comparison with state-of-the-art GeO x IL is also reported besides establishing correlations between band-edge interface trap density ( ${D}_{\text {it}}$ ), mobility ( $\mu$ ), and threshold voltage ( ${V}_{T}$ ) instability. Ultrafast measure-stress-measure (UF-MSM), ultrafast measure-stress-detrap-measure (UF-MSDM), stress-induced-leakage-current (SILC), direct-current current–voltage (DCIV), split capacitance–voltage ( ${C}$ – ${V}$ ), and low-temperature full conductance techniques along with a compact model demonstrate that: 1) trap generation occurs at IL/high- ${k}$ interface during stress; 2) an increase in $\mu$ with reduction in ${D}_{\text {it}}$ does not guarantee better reliability, i.e., ${V}_{T}$ shift and $\mu$ are uncorrelated due to their dependence on separate regions of the gate stack; 3) contributions to total ${V}_{\text {T}}$ degradation from trapping and generated traps are mutually exclusive; 4) UF-MSDM is a powerful tool to estimate trap generation; and 5) ${V}_{T}$ degradation is directly proportional to high- ${k}$ thickness, varies inversely with IL thickness, and reduces with annealing.

Effect of incorporation of nitrogen atoms in Al2O3 gate dielectric of wide-bandgap-semiconductor MOSFET on gate leakage current and negative fixed charge

We performed first-principle calculations to investigate the effect of incorporation of N atoms into Al2O3 gate dielectrics. Our calculations show that the defect levels generated by VO in Al2O3 are the origin of the stress-induced gate leakage current and that VOVAl complexes in Al2O3 cause negative fixed charge. We revealed that the incorporation of N atoms into Al2O3 eliminates the VO defect levels, reducing the stress-induced gate leakage current. Moreover, this suppresses the formation of negatively charged VOVAl complexes. Therefore, AlON can reduce both stress-induced gate leakage current and negative fixed charge in wide-bandgap-semiconductor MOSFETs.

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10−17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (EOX-Measure) were experimentally determined for fabricated devices.

Improved reliability characteristics of Ge MOS devices by capping Hf or Zr on interfacial layer

Ultralow equivalent oxide thickness and excellent reliability characteristics in Ge MOS devices with ZrO2 gate dielectrics are achieved by capping Hf or Zr on interfacial layer. Device with a Hf-cap layer demonstrates the lowest interface trap density and stress-induced leakage current. On the other hand, device with a Zr-cap layer exhibits the lowest hysteresis effects and stress-induced voltage shifts. The HfGeOx IL of high quality and ZrGeOx IL with few oxide traps are promising to improve reliability characteristics in Ge MOS devices.