Abstract

This paper presents a new attempt to further understand negative bias temperature instability (NBTI) stress in semiconductor devices. NBTI impact has been experimentally investigated on both p-substrate MOS (nMOS-capacitor) and nMOS transistors under accumulation condition, and new findings have been revealed. Indeed, nMOS-capacitor’s flat band shift ( $\boldsymbol {\Delta }\text{V}_{\mathbf {FB}}$ ) under NBTI stress has disclosed that time exponent ( ${n}$ ) and activation energy ( ${\mathbf{E}}_{\mathbf{a}}$ ) do vary with applied voltage stress pointing out to the contribution of two components, interface ( $\text{N}_{\mathbf {IT}}$ ) and oxide ( $\text{N}_{\mathbf {OT}}$ ) traps. Besides, the threshold electric field delimiting NBTI and stress induced leakage current can be well established. These findings have been confirmed by the appearance of a turn-around effect in nMOS transistors under NBTI stress. Moreover, charge pumping characterization has unveiled that NBTI degradation in nMOS transistor goes through two stages. First, only $\text{N}_{\mathbf {IT}}$ is created, then simultaneous generation of $\text{N}_{\mathbf {IT}}$ and $\text{N}_{\mathbf {OT}}$ takes part.

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