A 65nm test structure for the analysis of NBTI induced statistical variation in SRAM transistors

Abstract

We present the results of a test structure that allows to measure the variation of SRAM p-MOS and n-MOS transistors in a dense environment and to apply Negative Bias Temperature Instability (NBTI) stress on the p-MOS transistors. The threshold voltage (Vth) and drain current (Id) distributions of p-MOS SRAM transistors pre and post NBTI Stress are measured and analyzed. The probability density functions (PDF) of both transistor parameters Vth and Id follow a Gaussian distribution pre and post NBTI stress, but the difference in the transistor parameters of an individual device is not Gaussian distributed. The standard deviation in the difference of Vth is about 50% of the mean for the small SRAM p-MOS transistor. The impact of the additional variation induced by NBTI stress is shown for the Static Noise Margin of a 6-T SRAM cell.