Strained Silicon MOSFETs Research Articles

Strained SI/SIGE/SI Nano-Channel Hoi Mosfet

Strained Si technology has headed in the development of single or dual channel strained silicon MOSFETs devices. Comprehending the need of advancement in recent technologies with miniaturized features, developing a novel MOSFET on ultrathin double strained Si with strained SiGe sandwiched in between and forming a tri-channel MOSFET has been the crux of this present research. Incorporation of quantum carrier confinement effect on the ultrathin dual strained Si layers in the channel has been implemented to counterbalance the threshold voltage roll-off induced by the strained layers. A comparison of the conventional strained silicon on relaxed silicon-germanium with double strained silicon channel MOSFET has been perceived leading to eloquent drain current enhancement of ~49% with a small reduction in the threshold voltage caused by the additional bottom strained Si layer. Further, 100nm and 50nm channel length have been compared and a superior device characteristic for the reduced device dimension is attained as the prominence of velocity overshoot is more in short channel device approaching to quasi-ballistic transport in the channel region

Performance analysis of nanoscale double gate strained silicon MOSFET with high k dielectric layers

This study presents a theoretical model to describe the combined characteristics of strained silicon nanoscale double gate MOSFET along with high k dielectric layer. Although a well- tempered MOSFET with strong gate electrostatics can be devised using high k gate material, lower conduction band offset (CBO) over silicon results in leakage and subsequent static power dissipation. The study shows that this effect can reduce the Ion/Ioff ratio to 2 × 102 with 2 nm thick TiO2 dielectric layer (k = 60) along with mobility degradation. Incorporating the effects of strained silicon and high k dielectrics in MOSFETs exhibits bandstructure alteration and increase in CBO. This inhibits carrier tunnelling causing leakage with restoration of Ion/Ioff ratio to 4.5 × 106. The mobility can also be improved along with the maintenance of effective gate electrostatics. Thus the study illustrates the possibility of designing the nanoscale MOS devices with all the essential characteristics without trade-off over other performance parameters.

Physically based analytical model for plateau in gate C-V characteristics of strained silicon pMOSFET

A physically based analytical model was developed to predict the performance of the plateau observed in the gate C-V characteristics of strained-Si/SiGe pMOSFET. Experimental results were used to validate this model. The extracted parameters from our model were t OX=20 nm, N D=1×1016 cm−3, t SSi=13.2 nm, consistent with the experimental values. The results show that the simulation results agree with experimental data well. It is found that the plateau can be strongly affected by doping concentration, strained-Si layer thickness and mass fraction of Ge in the SiGe layer. The model has been implemented in the software for strained silicon MOSFET parameter extraction, and has great value in the design of the strained-Si/SiGe devices.

Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs

This paper investigates the electrical performance improvements induced by appropriate strain conditions in n-type InAs nanowire tunnel FETs in the context of a systematic comparison with strained silicon MOSFETs. To this purpose, we exploited a 3-D simulator based on an eight-band <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k p</b> Hamiltonian within the nonequilibrium Green function formalism. Our model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the band structure. The effect of acoustic- and optical-phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in n-type InAs tunnel FETs induce a remarkable enhancement of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> with a small degradation of the subthreshold slope, as well as large improvements in the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> versus I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> tradeoff for low I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> values. Hence, an important widening of the range of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> values where tunnel FETs can compete with strained silicon MOSFETs is obtained.

Impact of Strain and Channel Thickness on Performance of Biaxial Strained Silicon MOSFETs

In this paper the impact of strain and channel thickness on the performance of biaxial strained silicon MOSFET with 40 nm channel length has been analyzed by simulation in TCAD Sentaurus Simulator. With the increase in the mole fraction of germanium at the interface of the channel region, the strain in the silicon channel increases and with it the mobility of the carriers increases and thus the drain current increases. The mole fraction in this paper is varied from 0 to 0.3. Other than mobility, the increase in strain also shows improvement in other performance parameters. The impact of variation in channel thickness on the functionality parameters of the MOSFET has also been analyzed. The channel thickness cannot be increased more than the critical thickness and therefore, in this paper the thickness is varied from 2nm to 20 nm. It is observed that beyond 10nm the performance improvement gets saturated and therefore the critical thickness for the channel of this structure is 10nm..

Two-dimensional analytical models for asymmetric fully depleted double-gate strained silicon MOSFETs

This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and drain-induced barrier-lowering of CMOS-based devices in nanometre scale.

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson's equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.

Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics

As gate dielectrics are scaled to a few atomic layers and the channel doping is increased to mitigate short channel effects, high vertical electric fields cause considerable mobility degradation through surface-roughness scattering in silicon MOSFETs. This high-field mobility degradation is known to influence the harmonic distortion through higher order derivatives of the drain current. Failure to take these higher order derivatives into account can cause significant error in the predictive evaluation of linearity ( V IP 3) in MOSFETs. Electrical measurements are used to extract the 2nd order mobility degradation factor ( θ 2) from strained silicon MOSFETs fabricated on silicon germanium strain relaxed buffers with 15%, 20% and 25% germanium. Linearity and high-field mobility degradation are shown to be independent of strain in spite of atomic force microscopy measurements showing that the amplitude of the root-mean-square surface roughness increases with the germanium content. It is also shown that θ 2 is required for accurate modelling of linearity. The impact of oxide thickness on linearity is also investigated through θ 2. In this paper, an analytical relationship between θ 2 and the effective oxide thickness is developed and validated by electrical measurements on MOSFETs with different oxide thicknesses and θ 2 values from the literature. Using the extracted θ 2 values as inputs to analytical MOSFET models, a correlation between the oxide thickness and linearity is analyzed.

Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers

A comprehensive quantum anisotropic transport model for holes was used to study silicon PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of bulk silicon and silicon under field confinement as a twodimensional quantum gas are computed using the pseudopotential method and a six-band stress-dependent k.p Hamiltonian. Anisotropic scattering is included in the momentum-dependent scattering rate calculation. Mobility is obtained from the Kubo-Greenwood formula at low lateral field and from the fullband Monte Carlo simulation at high lateral field. Using these methods, a comprehensive study has been performed for both uniaxial and biaxial stresses. The results are compared with device bending data and piezoresistance data for uniaxial stress, and device data from strained Si channel on relaxed SiGe substrate devices for biaxial tensile stress. All comparisons show a very good agreement with simulation. It is found that the hole band structure is dominated by 12 wings, where mechanical stress, as well as the vertical field under certain stress conditions, can alter the energies of the few lowest hole subbands, changing the transport effective mass, density-of-states, and scattering rates, and thus affecting the mobility

Strained-silicon MOSFETs for analog applications: utilizing a supercritical-thickness strained Layer for low leakage current and high breakdown Voltage

Strained-silicon MOSFETs with both high breakdown voltage and low leakage current needed for RF/analog applications were investigated. Proper control of junction-depth profile and strained-silicon-layer thickness significantly improved transconductance, on resistance, and leakage current. Breakdown voltage of strained-silicon MOSFETs was the same as silicon MOSFETs even at elevated temperatures. RF/analog performances, such as cutoff frequency and 1/f noise, were improved by this technology while keeping high-driving-voltage capability.

Controlled misfit dislocation technology in strained silicon MOSFETs

In this paper, we report new process integration flows to fabricate strained-Si nMOSFETs having thicker strained-Si grown on a relaxed Si0.8Ge0.2 virtual substrate. For the same device parameters and process condition, a device with this advanced integration flow (sample B) starting epitaxial strained-Si layers after shallow trench isolation and well implantation is shown having a 70% enhancement in effective electron mobility compared to the Si control device. Devices with conventional process sequences (sample A) exhibit a larger leakage current and up to 50% device failure. The leakage mechanism in sample A due to misfit dislocation-induced leakage paths is clearly demonstrated from the photon emission microscopy (PEM) measurement. Improved characteristics in sample B indicate that devices with new process sequences exhibit controlled misfit dislocations in strained-Si layers and show a greater flexibility for developing high-performance strained-Si CMOS.

Time-Resolved Measurements of Self-Heating in SOI and Strained-Silicon MOSFETs Using Photon Emission Microscopy

A simple noninvasive optical technique for characterization of self-heating dynamics in advanced metal-oxide-semiconductor field-effect transistors is reported for the first time. The technique uses time-resolved photon emission microscopy to measure the temperature-dependent luminescence of off-state leakage current. It measures the temperature of the device channel, independent of surrounding materials or interconnects. The technique has been used to measure, for the first time, self-heating dynamics in silicon-on-insulator and strained-silicon n-field-effect transistors.

Ballistic transport in high electron mobility transistors

A general FET model that was previously used for MOSFETs is applied to high electron transistors (HEMTs), and the results are compared with experimental data for a sub-50 nm InAlAs-InGaAs HEMT. The results show that nanoscale HEMTs can be modeled as an intrinsic transistor with extrinsic source/drain series resistances. We also examine the ballistic mobility concept, a technique proposed for extending the drift-diffusion model to the quasi-ballistic regime. Comparison with a rigorous model shows that under low drain bias the concept, although nonphysical, can be used to understand the experimental phenomena related to quasi-ballistic transport, such as the degradation of the apparent carrier in short channel devices. We also point out that the concept loses validity under high drain bias. The conclusions of this paper should be also applicable to other nanoscale transistors with high carrier mobility, such as carbon nanotube FETs and strained silicon MOSFETs.

Device and circuit performance of SiGe/Si MOSFETs

It is shown that a 4-fold improvement in static and dynamic CMOS circuit performance can be achieved by the introduction of strained silicon MOSFETs. A 2-fold improvement is obtained using pseudomorphic SiGe pMOSFETs in static CMOS. The industry standard compact model BSIM3v3 is able to capture the features of buried channel and surface channel SiGe based MOSFETs for SPICE simulations. TCAD shows that surface channel strained silicon MOSFETs offer better n-channel performance than buried channel devices, while p-channel devices buried up to 4 nm may outperform surface channel pMOSFETs. The impact of achievable mobility on device design and performance is presented.