Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics

Abstract

As gate dielectrics are scaled to a few atomic layers and the channel doping is increased to mitigate short channel effects, high vertical electric fields cause considerable mobility degradation through surface-roughness scattering in silicon MOSFETs. This high-field mobility degradation is known to influence the harmonic distortion through higher order derivatives of the drain current. Failure to take these higher order derivatives into account can cause significant error in the predictive evaluation of linearity ( V IP 3) in MOSFETs. Electrical measurements are used to extract the 2nd order mobility degradation factor ( θ 2) from strained silicon MOSFETs fabricated on silicon germanium strain relaxed buffers with 15%, 20% and 25% germanium. Linearity and high-field mobility degradation are shown to be independent of strain in spite of atomic force microscopy measurements showing that the amplitude of the root-mean-square surface roughness increases with the germanium content. It is also shown that θ 2 is required for accurate modelling of linearity. The impact of oxide thickness on linearity is also investigated through θ 2. In this paper, an analytical relationship between θ 2 and the effective oxide thickness is developed and validated by electrical measurements on MOSFETs with different oxide thicknesses and θ 2 values from the literature. Using the extracted θ 2 values as inputs to analytical MOSFET models, a correlation between the oxide thickness and linearity is analyzed.