Steep-slope Transistors Research Articles

Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade.

Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InxGa1-xAsySb1-y/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essential to verify the fundamental physics of device operation, and thus imperative for taking the III-V TunnelFETs to the next level.

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursued approaches to achieve such a subthermionic subthreshold swing consist in alternative carrier injection mechanisms, like quantum mechanical band-to-band tunneling (BTBT) in Tunnel FETs or abrupt phase-change in metal-insulator transition (MIT) devices. The strengths of the BTBT and MIT have been combined in a hybrid device architecture called phase-change tunnel FET (PC-TFET), in which the abrupt MIT in vanadium dioxide (VO2) lowers the subthreshold swing of strained-silicon nanowire TFETs. In this work, we demonstrate that the principle underlying the low swing in the PC-TFET relates to a sub-unity body factor achieved by an internal differential gate voltage amplification. We study the effect of temperature on the switching ratio and the swing of the PC-TFET, reporting values as low as 4.0 mV/decade at 25 °C, 7.8 mV/decade at 45 °C. We discuss how the unique characteristics of the PC-TFET open new perspectives, beyond FETs and other steep-slope transistors, for low power electronics, analog circuits and neuromorphic computing.

(Invited) Recent Progress in Vertical Si/III-V Tunnel FETs: From Fundamentals to Current-Boosting Technology

Inherent issue for low-power LSI is lowering supply voltage of transistor while beating physical limit of subthreshold slope (SS = 2.3 k BT/q = 60 mV/dec) [1]. Otherwise, this limitation will stop further scaling of the power consumption even if a multi-gate architecture and III-V/Ge channels are implemented [2-4]. The steep-slope transistors such as tunnel FETs (TFETs) and impact ionization FETs have therefore been proposed to overcome the limitation and to reduce supply voltage to sub-0.5 V in future LSI. The tunneling transistors are most promising switching devices because of possibility for lower SS than 60 mV/dec. and better compatibility with conventional integration process. However, there are some difficulties in decreasing SS while increasing tunneling current as high as that of conventional FETs. Recently, we reported on new tunnel junction based on III-V/Si interface [4,5] which is formed by selective-area growth of III-V nanowires (NWs) on Si [6-8], and demonstrated vertical TFETs with steeper SS [9,10]. This new tunnel junctions can inherently forms abrupt heterojunction regardless of precise doping because the band discontinuity is determined only by the offset of each III-V and Si. Thus, good gate-electrostatic control and depletion-width control for the tunnel transport is defined only by the III-V channel region regardless of degeneration of source materials. Here we report on recent progress in the vertical TFETs using III-V NW/Si heterojunction and discuss some current-boosting technology such as strain and other technique. As for integration of III-V NWs on Si, selective-area growth has no thick buffer layer, thus the III-V NWs/Si interface is able to show unique band structures. The narrow gap III-Vs such as InAs and In0.7Ga0.3As NWs, for instance, exhibits staggered-Type II band structure when the n-type NWs are formed on p-Si substrates regardless precise doping [4,5]. Thus, we integrated InGaAs NWs on Si substrate by utilizing specific growth sequence to align vertical NWs [8]. Sn was used for n-type dopant, and Zn-pulse doping technique [10] was used to make pseudo intrinsic layer as channel region. The formation of intrinsic layer in such small NW-volume would be very important to induce large internal electrical field at the InGaAs/Si heterojunction. The length of the Zn-pulse doped region correspond to channel-length (200 nm-ling in this case). The vertical TFET with a single vertically aligned n+-InGaAs/Zn-pulse doped InGaAs axial NW on a p-Si substrate was firstly demonstrated. The device process was reported elsewhere [4,5]. The channel length was 200 nm. In the TFET using the bare InGaAs NW, the tunneling current under revise bias was modulated by gate bias with SS of 80 – 90 mV/dec, and the ION was 2.7 nA/µm at VDS = 0.50 V. With decreasing VDS, the SS become steeper than 60 mV/dec. at low drain current region. The minimum SS was around 50 mV/dec. at VDS= 0.10 V. As for current boosting technology, channel length scaling was characterized [5]. The ION was 100 times enhanced with decreasing the channel length to 50 nm, and the SS decreased to 30 mV/dec. at VDS = 0.10 V. This indicated that the drain end should be close to the tunnel junction width. Next, strain effect was characterized by using InGaAs/InP core-shell nanowire structure. Switching behavior with a SS of 42 mV/dec was obtained under reverse bias direction. This switching characterization appeared at as low as VDS of 10 mV. The SS of the TFET exhibits steeper SS behavior under various VDS. The ION for InGaAs/InP core-shell NW/Si TFET was 10 times higher than that of the bare InGaAs NW/Si TFET. The benefit of InP shell layer is improvement of SS and enhancement of ION. The InP shell layer act as passivation effect on the semiconductor/oxide interface. TEM analysis revealed the large compressive strain was induced at the near InGaAs NW/Si, which ascribes that the uniaxial compressive strain decrease effective band gap of InGaAs/Si while enhancing tunneling probability. Reduction in effective band gap of tunnel junction can partly enhance the tunneling current, but the tunneling leakage at source/channel region was increased degrading SS. Thus, further additional technology to enhance the tunneling current will be discussed.

Revisiting the Theory of Ferroelectric Negative Capacitance

In this paper we revisit the theory of negative capacitance, in a (i) standalone ferroelectric, (ii) ferroelectric-dielectric, and (iii) ferroelectric-semiconductor series combination, and show that it is important to minimize the total Gibbs free energy of the combined system (and not just the free energy of the ferroelectric) to obtain the correct states. The theory is explained both analytically and using numerical simulation, for ferroelectric materials with first order and second order phase transitions. The exact conditions for different regimes of operation in terms of hysteresis and gain are derived for ferroelectric-dielectric combination. Finally the ferroelectric-semiconductor series combination is analyzed to gain insights into the possibility of realization of steep slope transistors in a hysteresis free manner.

Enabling New Computation Paradigms with HyperFET - An Emerging Device

High power consumption has significantly increased the cooling cost in high-performance computation stations and limited the operation time in portable systems powered by batteries. Traditional power reduction mechanisms have limited traction in the post-Dennard Scaling landscape. Emerging research on new computation devices and associated architectures has shown three trends with the potential to greatly mitigate current power limitations. The first is to employ steep-slope transistors to enable fundamentally more efficient operation at reduced supply voltage in conventional Boolean logic, reducing dynamic power. The second is to employ brain-inspired computation paradigms, directly embodying computation mechanisms inspired by the brains, which have shown potential in extremely efficient, if approximate, processing with silicon-neuron networks. The third is “let physics do the computation”, which focuses on using the intrinsic operation mechanism of devices (such as coupled oscillators) to do the approximate computation, instead of building complex circuits to carry out the same function. This paper first describes these three trends, and then proposes the use of the hybrid-phase-transition-FET (Hyper-FET), a device that could be configured as a steep-slope transistor, a spiking neuron cell, or an oscillator, as the device of choice for carrying these three trends forward. We discuss how a single class of device can be configured for these multiple use cases, and provide in-depth examination and analysis for a case study of building coupled-oscillator systems using Hyper-FETs for image processing. Performance benchmarking highlights the potential of significantly higher energy efficiency than dedicated CMOS accelerators at the same technology node.

A steep-slope transistor based on abrupt electronic phase transition.

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (‘sub-kT/q') and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistor's source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

(Invited) Vertical Tunnel FETs Using III-V Nanowire/Si Heterojunctions

A main goal of future electronic circuits is lower huge power consumption of LSIs while enhancing the chip performance. The Si-CMOS technologies are expected to change their gate-architecture, channel material, and transport mechanism to overcome the apparently-paradoxical demands which is owing to the inherent issues in miniaturization of Si MOSFETs. Enhanced short-channel effect and leakage current is emerged problem in further scaling of the transistor size. To avoid these issues, the gate structure have already changed into fin architecture [1] and will shifted to gate-all-around (GAA) [2] or surrounding-gate structure [3]. As for channel materials, III-V and Ge are promising alternative channels [4,5] because of higher carrier mobility and low electron/hole effective mass achieving higher ON-state current under lower bias. Since these materials tend to exhibit slightly high leakage current due to tunneling leakage, multi-gate architecture for these channel would necessary for decreasing leakage current. Furthermore, the inherent mobility mismatch between the III-V and Ge will be bottleneck in device-integration scheme to match current density. In near future, the III-V channel has no other choice except for vertical channel architecture to avoid the issue. In this regard, a co-integration technique of vertical III-V channel with p-channel Ge will be required for Si-CMOS. Final target is beating physical limit of conventional MOSFET especially subthreshold slope (SS) due to carrier thermal diffusion (SS = 2.3 k BT/q = 60 mV/dec). This limitation will stop further scaling of the power consumption even if a multi-gate architecture and III-V/Ge channel are applied. The steep-slope transistors such as tunnel FETs (TFETs) and impact ionization FETs [6] have therefore been proposed to overcome the limitation and to reduce supply voltage to sub-0.5 V in future LSI. These distinct features should be mutually addressed as extended CMOS technologies. In this regard, the selective-area epitaxy of III-Vs on Si will play an important role as integration technique of vertical III-V channels on Si and Ge, and the excellent III-V/Si heterojunction can assist to connect these challenges smoothly. In this paper, we review recent advances in direct integration of vertical III-V nanowire (NW)-channel on Si and FET application such as vertical III-V NW surrounding-gate transistors (SGTs) and tunneling FET (TFETs) using III-V NW/Si heterojunctions. In addition to the high-performance vertical FET application using the III-V nanowire-channel on Si, the III-V/Si heterojunction, which is formed underneath the small footprint of the III-V nanowire, is a promising junction for the use of steep-SS switches because this heterojunction shows preudo-staggered Type-II band discontinuity in the case of the n-III-V nanowire/p+ -Si heterojunctions. Under the reverse bias condition, a large Zener current depending on the carrier concentration of p-Si occurs, indicating that this current is modulated by the gate bias. Once the Fermi level is laid in the valence band in p-Si with a high carrier concentration, band-to-band tunneling appears under the forward bias. In case of a vertical steep-SS switch using the III-V nanowire/Si heterojunction, controlling the series resistance is important to achieve a steeper SS (< 60 mV/dec) because the SS is the function of VG and VDS [7]. This means a large electrical field should be induced at the heterojunction or channel region under a lower VG and VDS. In this regard, reducing the diameter of the heterojunction to avoid the trap-assisted tunneling process via defect level and forming an intrinsic layer are important for obtaining steep SS property. The device using an InAs nanowire (30 nm in diameter)/Si heterojunction demonstrated a steep SS (minimum SS = 12 mV/dec) at room temperature [7, 8]. [1]. I. Ferain et al., Nature 479 (2011) 310. [2]. J. J. Gu et al., IEEE IEDM Tech. Dig. 769 (2011). [3]. H. Takato et al., IEEE TED 38 (1991) 573. [4]. J. A. del Alamo, Nature 479 (2011) 317. [5]. H. Riel et al., MRS Bulletin 39 (2014) 668. [6]. A. M. Ionescu et al., Nature 479 (2011) 329. [7]. K. Tomioka et al., VLSI Symp. Tech. Dig. (2012) 47 [8]. K. Tomioka et al., Nano Lett. 13 (2013) 5822.

Ferroelectricity of HfZrO&lt;sub&gt;2&lt;/sub&gt; in Energy Landscape With Surface Potential Gain for Low-Power Steep-Slope Transistors

The corresponding energy landscape and surface potential are deduced from the experimental ferroelectricity of HfZrO2 (HZO) for low-power steep-slope transistor applications. The anti-ferroelectric (AFE) in annealed 600°C HZO extracted electrostatic potential gain from the measured polarization hysteresis loop and calculated subthreshold swing 33 mV/dec over six decades of $I_{\rm DS} $ . A feasible concept of coupling the AFE HZO is experimentally established with the validity of negative capacitance and beneficial for steep-slope FET development in future generation.

Two-Dimensional Heterojunction Interlayer Tunneling Field Effect Transistors (Thin-TFETs)

Layered 2-D crystals embrace unique features of atomically thin bodies, dangling bond free interfaces, and step-like 2-D density of states. To exploit these features for the design of a steep slope transistor, we propose a Two-dimensional heterojunction interlayer tunneling field effect transistor (Thin-TFET), where a steep subthreshold swing (SS) of $\sim 14$ mV/dec and a high on-current of $\sim 300~\mu $ A/ $\mu $ m are estimated theoretically. The SS is ultimately limited by the density of states broadening at the band edges and the on-current density is estimated based on the interlayer charge transfer time measured in recent experimental studies. To minimize supply voltage $\mathrm{V}_{DD}$ while simultaneously maximizing on currents, Thin-TFETs are best realized in heterostructures with near broken gap energy band alignment. Using the WSe2/SnSe2 stacked-monolayer heterostructure, a model material system with desired properties for Thin-TFETs, the performance of both ${n}$ -type and ${p}$ -type Thin-TFETs is theoretically evaluated. Nonideal effects such as a nonuniform van der Waals gap thickness between the two 2-D semiconductors and finite total access resistance are also studied. Finally, we present a benchmark study for digital applications, showing the Thin-TFETs may outperform CMOS and III–V TFETs in term of both switching speed and energy consumption at low-supply voltages.

Tunnel FET RF Rectifier Design for Energy Harvesting Applications

Radio-frequency (RF)-powered energy harvesting systems have offered new perspectives in various scientific and clinical applications such as health monitoring, bio-signal acquisition, and battery-less data-transceivers. In such applications, an RF rectifier with high sensitivity, high power conversion efficiency (PCE) is critical to enable the utilization of the ambient RF signal power. In this paper, we explore the high PCE advantage of the steep-slope III-V heterojunction tunnel field-effect transistor (HTFET) RF rectifiers over the Si FinFET baseline design for RF-powered battery-less systems. We investigate the device characteristics of HTFETs to improve the sensitivity and PCE of the RF rectifiers. Different topologies including the two-transistor (2-T) and four-transistor (4-T) complementary-HTFET designs, and the n-type HTFET-only designs are evaluated with design parameter optimizations to achieve high PCE and high sensitivity. The performance evaluation of the optimized 4-T cross-coupled HTFET rectifier has shown an over 50% PCE with an RF input power ranging from -40 dBm to -25 dBm, which significantly extends the RF input power range compared to the baseline Si FinFET design. A maximum PCE of 84% and 85% has been achieved in the proposed 4-T N-HTFET-only rectifier at -33.7 dBm input power and the 4-T cross-coupled HTFET rectifier at -34.5 dBm input power, respectively. The capability of obtaining a high PCE at a low RF input power range reveals the superiority of the HTFET RF rectifiers for battery-less energy harvesting applications.

Tunnel field-effect transistor using InAs nanowire/Si heterojunction

We report on fabrication of tunnel field-effect transistor with III-V nanowire (NW)/Si heterojunction and surrounding-gate structure. The device fabricated by selective-area growth of an n+-InAs/undoped-InAs axial NW on a p+-Si(111) substrate showed switching behavior with an average subthreshold slope (SS) of 104 mV/dec under reverse bias condition. The switching behavior appeared under small supply voltage (Vds=50 mV). Transmission electron microscopy revealed misfit dislocation formed at the interface degraded the SS and ON-state current. Coherent growth without misfit dislocations would promise realization of steep-slope transistor with a SS of &amp;lt;60 mV/dec.