Statistical Compact Model Research Articles

Statistical Compact Modeling With Artificial Neural Networks

This work proposes a statistical modeling approach for the artificial neural network (ANN) based compact model (CM). The method of retaining part of the network features of the nominal device and further finetuning the network parameters (variational neurons) is found to accurately reproduce the static variation. A mapping from process variation to network parameters is derived by combining the proposed variational neuron selection algorithm and the backward propagation of variance (BPV) method. In addition, a secondary classification of the selected variational neurons is applied to model the fabrication-induced correlation between n-and p-type devices. The NN-based statistical modeling approach has been well implemented and verified on the GAA simulation data and the 16nm node foundry FinFET, which indicates its great potential in modeling emerging and advanced device technology.

Unified RTN and BTI statistical compact modeling from a defect-centric perspective

In nowadays deeply scaled CMOS technologies, time-dependent variability effects have become important concerns for analog and digital circuit design. Transistor parameter shifts caused by Bias Temperature Instability and Random Telegraph Noise phenomena can lead to deviations of the circuit performance or even to its fatal failure. In this scenario extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at near threshold, nominal and accelerated aging conditions. Statistical modelling of RTN and BTI combined effects covering the full voltage range is presented. The results of this work suppose a complete modelling approach of BTI and RTN that can be applied in a wide range of voltages for reliability predictions.

Reliability-Aware Statistical BSIM Compact Model Parameter Generation Methodology

This article presents an accurate, reliability-aware statistical Berkeley short-channel IGFET Model 4 (BSIM4) compact model parameter generation methodology using the generalized lambda distribution (GLD) method. Using this methodology, compact model parameter sets can be generated “on the fly” beyond the limitation of the number of compact models extracted from the TCAD simulation. The generated unlimited parameter sets enable circuit designer for the statistical circuit simulation. An analytical model has been developed to interpolate TCAD simulation data points, which enables statistical compact model parameter sets to be generated at any aging level. The capability to generate such intermediate aging model parameters at trap densities that were not physically simulated has important application in statistical circuit simulation, opening up the possibility to include accurately reliability assessment in circuit design. An aging model that can transfer trap density to stress/aging time is an integral part of the presented methodology. The accuracy of the compact model parameter generation methodology is validated by comparing the new generated compact model parameter sets at an interpolated trap density, against physical “atomistic” 3-D TCAD simulation. The compact model parameter generation methodology enables the accurate investigation of the influence of statistical variability and bias temperature instability (BTI)-induced aging at circuit level.

Statistical compact model extraction for skew‐normal distributions

A technique to extract statistical model parameters for skewed Gaussian process variations is proposed. Statistical compact model extraction traditionally assumes that underlying process variations are Gaussian in nature. ON currents in certain high voltage technologies, which are linear in process deviations, show skew in their distribution and hence is indicative of skew in the underlying process variations. The use of skew-normal random variables is proposed to model such variations. Artificial neural networks (ANNs) are used to empirically model the functional relation of performance on process deviations and a framework to propagate skew-normal random variables through ANNs is proposed. A non-linear optimisation problem is formulated to extract the parameters that characterise the skew-normal process variations, with constraints imposed on the objective function to penalise any deviation from Gaussian variations. Results show that the extracted parameters, when simulated, match the performance parameter targets to within 3% for both Gaussian and skewed process variations.

TCAD simulations and accurate extraction of reliability-aware statistical compact models

In this paper, we focus on the TCAD simulation and accurate compact model extraction of the time evolution of statistical variability in conventional (bulk) CMOS transistors, due to bias temperature instability (BTI). The 25-nm physical gate length MOSFETs, typical for 20 nm bulk CMOS technology, are used as test-bed transistors to illustrate our approach. Statistical physical simulations of fresh devices and devices at initial, middle and final stages of BTI degradation are performed and the corresponding nominal and statistical compact models are extracted using a two-stage extraction strategy. The extracted compact models not only accurately capture time evolution of the statistical distribution of the key MOSFET figures of merit, but also the complex correlations between them. An excellent agreement with the original physical TCAD simulation results provides a high degree of confidence that the extracted compact models deliver accurate representation of the operation of each device for the purposes of reliable circuit simulation and verification.

A Physical Model for the Statistics of the Set Switching Time of Resistive RAM Measured With the Width-Adjusting Pulse Operation Method

The correlation between the set time ( $t_{\mathrm {\mathrm {set}}}$ ) and the initial off-state resistance ( $R_{\mathrm{\scriptscriptstyle OFF}}$ ) statistics for a Ti/ZrO2/Pt bipolar resistive random access memory device was investigated. The width-adjusting pulse operation method, which can significantly improve the switching uniformity, was used to accurately measure $t_{\mathrm {\mathrm {set}}}$ , and the gathered statistical data were analyzed using Weibull distributions. Both the Weibull slope ( $\beta _{t}$ ) and the scale factor ( $t_{\mathrm {\mathrm {set63\%}}}$ ) of $t_{\mathrm {\mathrm {set}}}$ distributions were found to increase logarithmically with $R_{\mathrm{\scriptscriptstyle OFF}}$ . The observed $t_{\mathrm {\mathrm {set}}}-R_{\mathrm{\scriptscriptstyle OFF}}$ interdependence provides a guideline in improving the switching uniformity and optimizing the tradeoff between set speed and disturb immunity. An analytical cell-based model was developed to explain the $R_{\mathrm{\scriptscriptstyle OFF}}$ -dependent $t_{\mathrm{\scriptscriptstyle SET}}$ statistics, which can be implemented in statistical compact models and circuit simulators for improving RRAM cell design and memory performances.

FinFET Centric Variability-Aware Compact Model Extraction and Generation Technology Supporting DTCO

In this paper, we present a FinFET-focused variability-aware compact model (CM) extraction and generation technology supporting design-technology co-optimization. The 14-nm CMOS technology generation silicon on insulator FinFETs are used as testbed transistors to illustrate our approach. The TCAD simulations include a long-range process-induced variability using a design of experiment approach and short-range purely statistical variability (mismatch). The CM extraction supports a hierarchical CM approach, including nominal CM extraction, response surface CM extraction, and statistical CM extraction. The accurate CM generation technology captures the often non-Gaussian distributions of the key transistor figures of merit and their correlations preserving also the correlations between process and statistical variability. The use of the hierarchical CM is illustrated in the simulation of FinFET-based SRAM cells and ring oscillators.

Influence of Transistors With BTI-Induced Aging on SRAM Write Performance

Write time is a critical component of memory performance, which often defines cycle time. In order to accurately predict static random access memory (SRAM) performance, it is also important to take temporal degradation effects into account. This paper investigates the influence of bias temperature instability induced transistor degradation on a dynamic write performance of 20 nm bulk CMOS SRAM. The circuit simulations are based on the comprehensive physical simulation of the aging process and on a very accurate statistical compact model extraction and generation technology. Several scenarios, which differ based on aging pattern of the cell, are investigated to identify the most important transistors and the corresponding critical aging conditions. Mismatch between the two inverters results in an imbalance of the cell, which enlarges the difference in write time between 0 and 1. Finally, we show a response surface of changes in write margin in response to different degradation levels in the ON and OFF transistors.

Compact MOSFET Modeling for Process Variability-Aware VLSI Circuit Design

This paper presents a systematic methodology to develop compact MOSFET models for process variability-aware VLSI circuit design. Process variability in scaled CMOS technologies severely impacts the functionality, yield, and reliability of advanced integrated circuit devices, circuits, and systems. Therefore, variability-aware circuit design techniques are required for realistic assessment of the impact of random and systematic process variability in advanced VLSI circuit performance. However, variability-aware circuit design requires compact MOSFET variability models for computer analysis of the impact of process variability in VLSI circuit design. This paper describes a generalized methodology to determine the major set of device parameters sensitive to random and systematic process variability in nanoscale MOSFET devices, map each variability-sensitive device parameter to the corresponding compact model parameter of the target compact model, and generate statistical compact MOSFET models for variability-aware VLSI circuit design.

Back-Gate Bias Dependence of the Statistical Variability of FDSOI MOSFETs With Thin BOX

The impact of back-gate bias on the statistical variability (SV) of FDSOI MOSFETs with thin buried oxide (BOX) is studied via 3-D “atomistic” drift-diffusion simulation. The impact of the principal sources of SV, i.e., random dopant fluctuations, line edge roughness, and metal gate granularity, on threshold voltage, drain-induced barrier lowering, and drive current is studied in detail. It is shown that reverse back-bias is beneficial in terms of reducing the dispersion of the off-current and the corresponding standby leakage power, whereas forward back-bias reduces the on -current variability. The correlation coefficients between relevant figures of merit and their trends against back-bias are also studied in detail, providing guidelines for the development of statistical compact models of thin-BOX FDSOI MOSFETs for low-standby-power circuit applications.

Statistical Compact Model Extraction: A Neural Network Approach

A technique for extracting statistical compact model parameters using artificial neural networks (ANNs) is proposed. ANNs can model a much higher degree of nonlinearity compared to existing quadratic polynomial models and, hence, can even be used in sub-100-nm technologies to model leakage current that exponentially depends on process parameters. Existing techniques cannot be extended to handle such exponential functions. Additionally, ANNs can handle multiple input multiple output relations very effectively. The concept applied to CMOS devices improves the efficiency and accuracy of model extraction. Results from the ANN match the ones obtained from SPICE simulators within 1%.

Accurate capturing of the statistical aspect of NBTI/PBTI variability into statistical compact models

In the contemporary and future MOSFETs, NBTI/PBTI-related charge trapping in the presence of underlying statistical variability gives rise to statistical degradation of the coresponding electrical characteristics and figures of merit. We present a framework that integrates the statistical aspect of the NBTI/PBTI degradation, obtained from large-scale 3D ‘atomistic’ device simulations, into statistical compact models. Through a selection of physically relevant compact model parameters, the resulting library of compact models provides high accuracy in representing the statistical NBTI/PBTI degradation effects, across a wide range of degradation conditions. This approach enables circuit designers to verify to what extent particular design solutions will meet the design specifications subject to progressive BTI degradation in the presence of statistical variability.

Statistical Variability in Fully Depleted SOI MOSFETs Due to Random Dopant Fluctuations in the Source and Drain Extensions

Simulations of up to 10 000 fully depleted thin-body silicon-on-insulator MOSFETs show that the standard deviation of the threshold voltage cannot be adequately used as a sole metric of device variability in such transistors. This is due to a sharp departure from normality of the threshold voltage distribution, and an enhanced influence of the source/drain-dopant fluctuations on the on-current and short-channel effects of the fully depleted thin-body silicon-on-insulator transistors. Both aspects have great ramifications for statistical compact models and for low-power SRAM designs.

Impact of statistical parameter set selection on the statistical compact model accuracy: BSIM4 and PSP case study

Statistical compact modeling (SCM) is necessary for variability aware design at nanometer regime. An extensive study has been carried out to evaluate the impact of the statistical parameter set selection on the statistical accuracy of two widely used industry standard compact models: BSIM4 and PSP. Different statistical parameter generation strategies have been employed to examine the impact of different statistical parameter selection on both device and circuit simulation accuracy.

A statistical-based material and process guidelines for design of carbon nanotubefield-effect transistors in gigascale integrated circuits

Carbon nanotube field-effect transistors (CNFETs) show great promise as buildingblocks of future integrated circuits. However, synthesizing single-walled carbonnanotubes (CNTs) with accurate chirality and exact positioning control has beenwidely acknowledged as an exceedingly complex task. Indeed, density and chiralityvariations in CNT growth can compromise the reliability of CNFET-based circuits. Inthis paper, we present a novel statistical compact model to estimate the failureprobability of CNFETs to provide some material and process guidelines for thedesign of CNFETs in gigascale integrated circuits. We use measured CNT spacingdistributions within the framework of detailed failure analysis to demonstrate thatboth the CNT density and the ratio of metallic to semiconducting CNTs playdominant roles in defining the failure probability of CNFETs. Besides, it is arguedthat the large-scale integration of these devices within an integrated circuit willbe feasible only if a specific range of CNT density with an acceptable ratio ofsemiconducting to metallic CNTs can be adjusted in a typical synthesis process.

Compact Modeling of Variability Effects in Nanoscale nand Flash Memories

This paper presents a thorough investigation of the main variability effects in nanoscale nand Flash memories, considering their impact on device operation by means of a statistical compact model for the memory array. The compact model allows the accurate simulation not only of the nand string current in read conditions, including parasitic capacitive couplings among neighboring cells, but also of cell program and erase. Changing the model parameters to account for their physical fluctuation in a Monte Carlo fashion, the impact of each variability source on the statistical dispersion of both neutral and programmed cell threshold voltage is obtained for state-of-the-art and next-generation technology nodes. The good agreement between modeling and experimental results and the low computational load make the proposed methodology a valid solution for the assessment of variability constraints on nand technology design.

Hierarchical Simulation of Statistical Variability: From 3-D MC With “ ab initio” Ionized Impurity Scattering to Statistical Compact Models

Quantum corrections based on density gradient formalism, recently introduced in the 3-D Monte Carlo (MC) module of the Glasgow “atomistic” simulator, are used to simultaneously capture quantum confinement effects as well as “ab initio” ionized impurity scattering. This has allowed us to consistently study the impact of transport variability due to scattering from random discrete dopants on the on-current variability in realistic nano-CMOS transistors. Such simulations result in an increased drain current variability when compared with the drift diffusion (DD) simulation. For the first time, a method that is used to accurately transfer the increased on-current variability obtained from the “ ab initio” MC simulations to the DD simulations is subsequently presented. The MC-corrected DD simulations are used to produce the target I-V characteristics from which the statistical compact models are extracted for use in preliminary design kits at the early stage of new technology development.

Parameter set and data sampling strategy for accurate yet efficient statistical MOSFET compact model extraction

Abstract This paper presents an effective statistical compact modelling strategy that can precisely capture a statistical set of MOSFET characteristics into industrial strength statistical compact models. 3D simulation of large statistical sample of microscopically different devices is required for statistical compact model extraction when studying the impact of variability in next CMOS technology generations on circuit and system design. For a particular nominal device design the statistical 3D physical simulations needs two orders of magnitude more CPU time compared to conventional TCAD simulations. A data sampling strategy is presented to reduce the number of bias points in simulated device characteristics used as extraction targets for statistical compact model parameter extraction. We show that for a well balanced set of statistical compact model parameters carefully chosen small number of strategic bias points in the simulated I–V characteristics of each microscopically different transistor is sufficient to capture accurately the statistical device behaviour. The corresponding increase in the RMS error is below 1% compared to results from comprehensive bias point set. The impact of the slight reduction of the compact model accuracy on the accuracy of statistical circuit simulation has also been investigated.

Statistical Compact Model Parameter Extraction by Direct Fitting to Variations

In this paper, a new method of statistical compact model parameter extraction is proposed and described in detail. The method is characterized in that the target of fitting is not the individual transistor, but statistically analyzed results (more specifically, principal components) of measured data. Variations of transistor characteristics can be translated into equivalent variations of compact model parameters by only one fitting step without repeating the parameter extraction procedure multiple times. Since the fitting is based on the response of a compact model to parameters, detailed information of the model is not necessary. The method has been applied to modeling the variations of metal-oxide-semiconductor field-effect transistor current versus voltage characteristics, and its validity has been confirmed.

IMPACT OF INTRINSIC PARAMETER FLUCTUATIONS IN NANO-CMOS DEVICES ON CIRCUITS AND SYSTEMS

Device parameter fluctuations, which arise from both the stochastic nature of the manufacturing process and more fundamentally from the intrinsic discreteness of charge and matter, are a dominant source of device mismatch in nano-CMOS devices, and a bottleneck to the future yield and performance of circuits and systems. The impact of such parameter fluctuations is investigated for circuits — with a specific exemplar of 6-T SRAM — whose devices scale from 35 nm gate length. We posit a change in design approach to include the use of statistical compact models as a starting point for the development of cell libraries containing fluctuation information necessary for design under the constraints of parameter fluctuations, and novel Technology Aided System Design tools.