Static Random Access Memory Research Articles

Memristor Crossbar Circuit for Ternary Content‐Addressable Memory with Fine‐Tuning Operation

Memristor‐based ternary content‐addressable memory (TCAM) has emerged as an alternative to conventional static random‐access memory (SRAM)‐based TCAM because of its high‐density integration and zero‐static energy consumption. Herein, 0T2R TCAM operation on a 32 × 32 passive memristor crossbar circuit is experimentally verified. The effective margin, which is the difference between the match case and 1‐bit mismatch case, is improved through precise tuning operations. Moreover, the number of mismatch bits and match cases can be accurately detected thanks to the linear relationship between the number of mismatch bits and match‐line current. In addition, the nonideal effects in the passive crossbar array including dynamic voltage drop and sneak current are analyzed through SPICE studies. These results indicate that the proposed TCAM operating conditions can ensure stable TCAM operation in larger arrays.

Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design

For low voltage CMOS static random access memory (SRAM) cells, the leakage current on bit-lines will slow down the reading operation and even lead to error reading. Herein we report a 4B4C circuit composed of 8T SRAM arrays, four bit-lines and four coupling capacitors to track and compensate the bit-line leakage current (BLLC). The assistant bit-lines are used to control the connection of capacitors. The coupling capacitors are used to compensate voltage losses caused by the BLLC, and improve the maximum tolerable current from primary bit-line. The timing diagram and output waveforms verify the compensatory effects of coupling capacitors. The 4B4C circuit shows fast reading operation and increases the maximum tolerable leakage current to 17.8 times compared with conventional circuit at FS process corner. The 4B4C circuit can keep 100% correct reading till 200 μA from Monte Carlo simulations. The 4B4C circuit enhances SRAM reading reliability and shows huge potential in very-large scale memory arrays.

CharTM: The dynamic stability characterization for memory based on tail distribution modeling

Dynamic stability has become a major constraint to static random access memory (SRAM) circuits design. In this paper, the relationship between the read/write delay and corresponding yield will be given by our CharTM, an unified memory yield analysis method by modeling the tail of performance distribution. In charTM, we design an efficient weighted regression-based high-dimensional meta-model to collect the tail samples without running simulations and construct the tail distribution by generalized Pareto distribution(GPD) with an adaptive tail fraction selection strategy to improve the accuracy in the high-sigma region. The effectiveness of CharTM is verified on bit cell, read, and write critical paths of an SRAM. The results show that the efficiency of CharTM exceeds that of a commercial yield analysis tool by 5.3–16.5 times on our validation cases with the same level of accuracy, and exceeds that of state-of-the-art methods by 13–82 times with much higher accuracy, especially on read and write paths.

Design of Cost-Efficient SRAM Cell in Quantum Dot Cellular Automata Technology

SRAM or Static Random-Access Memory is the most vital memory technology. SRAM is fast and robust but faces design challenges in nanoscale CMOS such as high leakage, power consumption, and reliability. Quantum-dot Cellular Automata (QCA) is the alternative technology that can be used to address the challenges of conventional SRAM. In this paper, a cost-efficient single layer SRAM cell has been proposed in QCA. The design has 39 cells with a latency of 1.5 clock cycles and achieves an overall improvement in cell count, area, latency, and QCA cost compared to the reported designs. It can therefore be used to design nanoscale memory structures of higher order.

High-performance and highly-stable soft error resistant 12T SRAM cell for space applications

In this paper, a high-performance and highly-stable soft error resistant 12T (HPHS12T) SRAM cell is proposed. Based on polarity reversal design and NMOS stacked structure, the proposed HPHS12T cell can recover from any single event upsets (SEU) induced at all its sensitive nodes and even single event multiple-node-upsets (SEMNU) induced at its internal storage node pair Q-QN, while also having the maximum read static noise margin (RSNM) and write noise margin (WNM), as well as excellent write-ability. Though the HPHS12T cell exhibits a larger static hold power, it has the best overall performance of all the other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed cell a better choice for space applications.

Influences of well contact on multiple-cell upsets in 28 nm SRAM

In order to study the effects of the feature size reduction and well contact placement on the characterization of topology patterns and the charge collection mechanism of device heavy ion single event multiple upset on a nanometer scale, the heavy ion single event effect experiment on the domestic 28 nm static random-access memory (SRAM) is carried out on the experimental platform of HI-13 heavy ion accelerator in Beijing. Based on the mapping relationship between the logical address and physical address of the device, the experimental data are processed, and the 28 nm SRAM heavy ion single event upset cross section curves, multiple upset percentage, and multiple upset topology patterns are obtained. The results are compared with those of heavy ion single event effect experiments in 65 nm SRAM, showing that under the influences of factors such as feature size reduction and lower operating voltage, the heavy ion single event upset threshold and the bit upset saturation cross section of 28 nm SRAM decrease significantly. In the direction perpendicular to the well, owing to the reduced 28 nm SRAM feature size, even if the single nucleon energy of the incident high LET (linear energy transfer) heavy ion is low, its deposited charge is sufficient to affect the three SRAM cells across the well direction due to the combined effect of ion track coverage, well potential modulation caused by the parasitic bipolar amplification effect and carrier diffusion, resulting in the fact that the 28 nm SRAM topology pattern has a shape of <i>n</i> rows × 3 columns, which poses new challenges and requirements for the anti-radiation hardened technology with scrubbing and EDAC (error detection and correction). Owing to the global well contact deployment, the charge deposited by the incident ions in the well far away from the well contact is difficult to discharge quickly, and the parasitic bipolar amplification effect lasts longer. The charge sharing competition between two p-channel metal oxide semiconductor in SRAM cell causes the single event upset recovery, which is the fundamental reason why the discontinuity of multiple upset topology pattern appears in 28 nm SRAM. This study provides a new anti-radiation hardened idea for suppressing the single event upset by using the parasitic bipolar amplification in the future.

Performance evaluation of SRAM design using different field effect transistors

SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it. Unlike Dynamic RAM, Static RAM uses a flip-flop circuit to store each data bit, whereas Dynamic RAM uses a capacitor to store the data bit. But capacitor has tendency of losing charge which requires periodic refreshment. Thus SRAM perform better and have more stability than DRAM especially in idle state. In this work, we analysed the performance of the SRAM cell which are built with different field effect transistors and calculated the Write and Read delays, PDP (Power Delay Product) and Static Noise Margin (SNM) for all types of transistors. SRAM cell which is based on the CNT technology with optimized parameters of CNT density, CNT diameter and CNTFET flat band voltage has the better performance and stability compared with other device technologies. Optimized CNTFET SRAM cell compared with the MOSFET based SRAM the write and read delays are improved by 85.8% and 94.3% respectively. All the simulations have been carried out using HSPICE tool for 32nm technology node.

Performance Analysis Of SRAM and Dram in Low Power Application

All electronic systems must function quickly in the current environment, and 80 percent of electronic chips have memory components. SRAM (Static Random Access Memory) has thus become a major key component in many VLSI Chips in order to reduce the size of the memory chips, to increase the speed, to reduce leakage current, and to increase the power efficiency. Due to its high storage density and quick access time, it has also become a popular data storage device. SRAM has been given priority in the research community due to the recent sharp development in low power and low voltage memory devices. In this study, the design and performance of SRAM and DRAM cells were analyzed. This paper outlines the development and application of modified 6T SRAM cell with increased power efficiency.

A Read-Decoupled Error-Tolerant 10T SRAM Cell in 32nm CMOS Technology

Stability of static random access memory (SRAM) cells has become a growing concern in the nanometer regime. In order to address this issue, this paper proposes a read-decoupled 10 transistor (10T) SRAM cell. The decoupled-read feature of the proposed 10T SRAM cell protects it from the read-disturbance problem, thereby achieving enhanced read stability. Additionally, the bit interleaving capability of the cell provides immunity to soft errors. The simulation is performed on TSPICE software using a 32 nm CMOS predictive technology model. The obtained results reveal that the read static noise margin - at 400 mV - of the proposed design is 4.77x and 1.38x larger compared to that of a 6T cell and the Schmitt-trigger based 10T cell, respectively. Moreover, the write power consumption in the proposed design is found to be 1.86x lesser than that of a 6T cell. Furthermore, the proposed circuit exhibits 3.47x lesser static power consumption compared to a 6T cell.

A New SRAM-Embedded Pixel Circuit That Modulates Accurately Gray Level for PWM-Driven Micro-LED Displays

A new analog pulse width modulation (A-PWM) pixel circuit is proposed for micro light-emitting diode (micro-LED) displays, which improves the accuracy of modulating gray level by efficient switching of its in-pixel static random access memory (SRAM). Varied gray levels are realized successfully with the integral of a constant current over corresponding designated duty for target gray. In practice, however, the imperfection of the current’s falling due to unavoidable switching delays results in nonlinear inaccuracy of displayed gray levels, undermining displaying quality. To remedy the problem, the proposed in-pixel SRAM is able to conduct faster switching than conventional pixel circuits for precise displaying of grays. The simulated results show the falling time is significantly reduced to 0.8ls from averaged 287ls of that without SRAM, obtained a near-constant gray output of 6.63nA*s/V. Based on experiments, the measured results show the DNL is improved from +0.05LSB-to-+0.78LSB to.0.09LSB-to-+0.14LSB, leading to the INL is reduced from the maximum +20.5LSB to +4.16LSB. In other words, the effectiveness offered by the proposed in-pixel SRAM in modulating accurately gray level is verified.

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3× Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Gain-cell embedded DRAM (GC-eDRAM) is a high-density logic-compatible alternative to conventional static random-access memory (SRAM) and embedded DRAM (eDRAM). However, GC-eDRAM suffers from a reduced data retention time (DRT) at deeply-scaled process nodes, leading to frequent power-hungry refresh operations. In order to reduce the refresh overhead, GC-eDRAM macros utilize external assist voltages which improve the bitcell write-ability, leading to an enhanced DRT. However, the requirement for external analog supply voltages creates additional overhead and is often impractical in the design of compact systems-on-chip (SoC). This work presents an on-chip write-assist technique implemented with a negative boosted bootstrap driver which generates the required wordline boosting on-chip without external components. The proposed circuitry is integrated compactly inside the GC-eDRAM macro to provide an area-efficient low-power solution which improves the bitcell’s write-ability and reduces its refresh requirement. A 128-kbit GC-eDRAM macro utilizing the proposed boosting circuitry has been fabricated in a 28-nm FD-SOI technology, demonstrating an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.3\times $ </tex-math></inline-formula> DRT improvement at only 2.5% area overhead.

Configurable and High-Throughput CIM SRAM for Boolean Logic Operation With 321 GOPS/kb and 164395.6 GOPS/mm2

In this letter, we propose a twin-operand computing method based on transforming a static random-access memory (SRAM) macro that can be used for image processing. The proposed cross-coupled 10T cell structure can be configured into a dual 4T structure, and the computational results can be stored in situ, thus significantly improving energy efficiency. Furthermore, unlike previous designs, the proposed computationin-memory (CIM) macro allows independent operands, where two operands are stored in dual 4T. Not only can it provide computational functions, but it can also double the storage density. The measurement results of a 55 nm CMOS prototype chip show that it achieves the highest throughput of 321 GOPS/Kb, 164395.6 GOPS/mm2, and 364.2 TOPS/W at 1.2 V.

A Novel Domino Logic Based on Floating-Gate MOS Transistors

Domino logic finds a wide variety of applications in both static and dynamic random-access memories and in high-speed microprocessors. However, the main limitation of the domino logic-circuit family is the trade-off between the noise immunity and speed. In order to resolve such a trade-off, this paper proposes a domino logic that is based on floating-gate MOS (FGMOS) transistors. Compact-form expressions are derived for the noise margins for the low and high inputs as well as the propagation delays. The proposed scheme is verified by simulation adopting the 45 nm CMOS predictive technology model (PTM) with a power-supply voltage of 1 V. The obtained results unveil that the proposed domino logic outperforms the conventional domino logic in terms of the power-delay product and the energy-delay product when realizing wide fan-in OR gates. The realized, with the proposed scheme, 16-input OR gate has an average power consumption of 3.7 µW and a propagation delay of 51 ps.

An Integrated Real-Time FMCW Radar Baseband Processor in 40-nm CMOS

In this paper, a pipelined frequency-modulated continuous-wave (FMCW) radar baseband processor applied to real-time applications is proposed and implemented in 40-nm CMOS technology. The FMCW radar signal processing time is analyzed according to the system specifications. On the basis of the theoretical analysis and systematic considerations, a pipelined baseband architecture with internal single-port static random access memory (SRAM) is employed. The baseband processor is mainly composed of two-dimensional fast Fourier transform (2D-FFT), two-dimensional constant false alarm rate (2D-CFAR), digital beam-forming (DBF), and memory control modules. The 2D-FFT module is structured with a pipelined scheme and avoids the waste of data transferring time between modules. The 2D-CFAR module is programmable for different applications. The designed address control is proposed to depose the edge cells. The processor occupies a core chip area of 3.353 mm ×3.353 mm and has been tested on the personal computer (PC) and field programmable gate array (FPGA) platform. The power consumption and processing time are also analyzed and compared with other works. The processor consumes 55.65 mW, including SRAMs. The processing time is 12.67 ms with the maximum window size and 256 targets when operating at 125 MHz. This time is estimated based on the assumption that each chirp lasts for 0.04096 ms, and data input takes 10.48 ms. Within this period, the range FFT is completed. The Doppler FFT, 2D-CFAR with the maximum window size, and DBF with 256 targets require 0.80 ms, 1.16 ms, and 0.23 ms respectively.

DESIGN OF A 6T SRAM CELL WITH MINIMAL POWER USING CADENCE VIRTUOSO

It has proven challenging for VLSI designers to lower leakage power at the nanoscale level. This is because high- end gadgets, battery-operated portable pads, and other communication tools are in high demand. Memories are made up of static RAM and dynamic RAM. SRAM has had a significant impact on the worldwide VLSI market sinceit is preferred over DRAM because to its rapid read and write access times. Using a 6T static random access memory cell, this study's novel approach to lowering leakage current at various technologies has been put forth. To reduce the 6T SRAM cell leaking power, three source biasing techniques are used. At 45 nanometer and 90 nm technology nodes, the three techniques are NMOS diode clamping, PMOS diode clamping, and NMOS-PMOS diode clamping. The implementation of a 6T SRAM cell using the Multiple Threshold CMOS (MTCMOS) technique at 45nm technology is also emphasised in this article. Using the cadence virtuoso tool, the simulation is completed and different power dissipations are examined for 45 nm and 90 nm technologies, respectively, at supply voltages of 0.45 V and 0.9 V. Comparing PMOS clamping to the other two suggested techniques, an average power reduction of 82.19% was observed.

High Dynamic Range Digital Neuron Core With Time-Embedded Floating-Point Arithmetic

Recently, many large-scale neuromorphic systems that emulate spiking neural networks have been presented. Biological evidence emphasizes the importance of the log-normal distribution of biological neural and synaptic parameters in the brain; however, this fact is easily ignored sometimes, and the parameters are excessively optimized to scale up a system. This is because high-precision parameters require floating-point arithmetic–an operation known to consume high-energy and result in a high implementation cost in digital hardware. In this study, we propose a novel neuron implementation model that enhances neural and synaptic dynamics using the time-embedded floating-point arithmetic for better biological plausibility and low-power consumption. The proposed algorithm enables sharing temporal information with a membrane potential by time-embedded floating-point arithmetic, thus minimizing the memory usage of the neural state. In addition, this method need not access the static random-access memory at every time step, thus reducing the dynamic power consumption, even with a floating-point precision neural and synaptic dynamics. Using the proposed model, we implemented a core group with a total of 8,192 neurons on a field-programmable gate array device, Xilinx XC7K160T. The core group is designed for use in large-scale neuromorphic systems. We tested the neuron model in a core under various experimental conditions.

A Comparative Analysis of FinFET Based SRAM Design

FinFETs are widely used as efficient alternatives to the single gate general transistor in technology scaling because of their narrow channel characteristic. The width quantization of the FinFET devices helps to reduce the design flexibility of Static Random Access Memory (SRAM) and tackles the design divergence between stable, write and read operations. SRAM is widely used in many medical applications due to its low power consumption but traditional 6T SRAM has short channel effect problems. Recently, to overcome these problems various 7T, 9T, 12T, and 14T SRAM architectures are designed using FinFET. This article provides a comprehensive survey of various designs of SRAM using FinFET. It offers a comparative analysis of FinFET technology, power consumption, propagation delay, power delay product, read and write margin. Additionally, the article presents the simulation of the 5T and 6T SRAM design using CMOS and FinFET for 14 nm technology using Microwind 3.8 simulation tool. The outcomes of the proposed SRAM design are compared with several recent designs based on power, delay, and, and various stability analysis parameters such as read, write and hold noise margin. Finally, the article discusses the challenges in SRAM design using FinFET and provides the future direction for optimization of accuracy, area, speed, delay, and cost of the FinFET-based SRAMs.

An 8kb RRAM-Based Nonvolatile SRAM with Pre-Decoding and Fast Storage/Restoration Time

Combining the advantages of low-power consumption of static random access memory (SRAM) with high stability and nonvolatile of resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell was proposed in this paper. In order to solve the problem that data cannot be stored when SRAM is powered off, RRAM technology was introduced into SRAM to realize an SRAM with nonvolatile function. The differential mode was adopted to improve the data restoration speed. Meanwhile, a pre-decoding technology was proposed to realize fast address decoding, and a voltage-mode sensitive amplifier was used to achieve fast amplification of two bit lines, so as to improve the reading speed of the memory. An 8kb nvSRAM was implemented with a CMOS 28 nm 1P9M process. The simulation results show that when the power supply voltage was 0.9 V, the static/read/write noise margin was 0.35 V, 0.16 V and 0.41 V, respectively. The data storage time was 0.21 ns, and restoration time was 0.18 ns. The time for the whole system to read 1 bit of data was 5.2 ns.

A gate leakage current-powered loadless 4T SRAM with immunity against random dopant fluctuation and surface roughness in silicon-silicon dioxide interface

The sensitivities of the data hold, read and write performances for the gate leakage-powered loadless 4T SRAM cell on the variations in the MOSFETs’ gate leakage currents are examined by SPICE Monte Carlo simulations in 32 nm technology. The standard deviations in the gate leakage current variations are taken from the device simulation results in which the variations are caused by the random dopant fluctuation and the surface roughness in silicon-silicon dioxide interface. It is shown that the static noise margin (SNM) in the data hold state is 60 mV at 1 V power supply voltage for the −5σ cell with the MOSFETs’ threshold voltage variations taken into consideration. The read SNM and the write SNM are shown to be 160 mV and 440 mV for the −5σ cell, respectively, which are better than the 6TSRAM cell.

Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature

An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.