Static Frequency Divider Research Articles

HIGH-PERFORMANCE Si and SiGe BIPOLAR TECHNOLOGIES AND CIRCUITS

In this paper we present Si and SiGe bipolar technologies and circuits suited for present and future high-performance communication systems. The silicon bipolar technology described has an implanted base and, without increase in process complexity in comparison to current production technologies, transit frequencies of 52 GHz and maximum oscillation frequencies of 65 GHz are achieved. The transistors of the described epitaxial SiGe-base technologies exhibit transit frequencies of 81 GHz and maximum oscillation frequencies of 95 GHz. Measurement results of circuits realized in these technologies for low power and high-speed applications are presented: a 43 GHz low power dynamic frequency divider, a 23 GHz monolithically integrated oscillator, a 40 Gb/s clock and data (CDR) recovery realized in the pure silicon bipolar technology, and a 53 GHz static frequency divider, a 79 GHz dynamic frequency divider and a 20 GHz/27 mW dual-modulus prescaler in the SiGe technology.

67-GHz static frequency divider using 0.2-μm self-aligned SiGe HBTs

A 67-GHz 1/4 static frequency divider using 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe heterojunction bipolar transistors, with a 122-GHz cutoff frequency, a 163-GHz maximum oscillation frequency, and an average emitter coupled logic gate delay time of 5.65 ps, was developed. The pretracking master-slave toggle flip-flop (MS-TFF) of the divider increases the maximum operating frequency to about 15% higher than that of a conventional MS-TFF, yet the power consumption of the divider is 175 mW, which is 1/5 that of comparable dividers, at a supply voltage of -5.2 V.

High-speed small-scale InGaP/GaAs HBT technology and its application to integrated circuits

We have developed the advanced performance, small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) by using WSi/Ti base electrode and buried SiO/sub 2/ in the extrinsic collector. The base-collector capacitance C/sub BC/ was further reduced to improve high-frequency performance. Improving the uniformity of the buried SiO/sub 2/, reducing the area of the base electrode, and optimizing the width of the base-contact enabled us to reduce the parasitic capacitance in the buried SiO/sub 2/ region by 50% compared to our previous devices. The cutoff frequency f/sub T/ of 156 GHz and the maximum oscillation frequency f/sub max/ of 255 GHz were obtained at a collector current I/sub C/ of 3.5 mA for the HBT with an emitter size S/sub E/ of 0.5/spl times/4.5 /spl mu/m/sup 2/, and f/sub T/ of 114 GHz and f/sub max/ of 230 GHz were obtained at I/sub C/ of 0.9 mA for the HBT with S/sub E/ of 0.25/spl times/1.5 /spl mu/m/sup 2/. We have also fabricated digital and analog circuits using these HBTs. A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB/spl middot//spl Omega/ with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed, low-power circuit applications.

Self-aligned selective-epitaxial-growth SiGe HBTs: process, device, and ICs

We review the fabrication process and device technologies of a high-speed self-aligned selective-epitaxial-growth (SEG) SiGe-base heterojunction bipolar transistor (HBT), and its potential application in ICs for optical-fiber-link systems. A 0.54-μm-wide SiGe base, self-aligned to the 0.14-μm-wide emitter to reduce collector capacitance, was selectively grown by using a UHV/CVD system. A self-aligned stacked metal/in situ doped poly-Si electrode technology enables low parasitic resistance, and allows the intrinsic base profile to be kept shallow, so it is well-suited to a SiGe-base HBT. A 2-μm-wide insulator refilled trench was introduced to reduce substrate capacitance. This SiGe HBT makes it possible to obtain 95-GHz cutoff frequencies and 97-GHz maximum oscillation frequencies, and ultra-high-speed emitter-coupled-logic (ECL) circuits with an 8-ps gate delay. The technology was applied in ICs required for optical-fiber-link systems, including a 1/8 static frequency divider with a maximum operating frequency of up to 50 GHz, a time-division multiplexer and a demultiplexer operating at 40 Gb/s, a preamplifier with a bandwidth of 35 GHz, an AGC amplifier core with a bandwidth of 32 GHz, and a decision circuit operating at 40 Gb/s.

A low-power 15-GHz frequency divider in a 0.8-μm silicon bipolar technology

In this paper, we present a low-power static frequency divider with a divide ratio of eight. It operates up to 15 GHz, consuming only 22 mA from a 3.6-V supply. The chip is manufactured in a 0.8-/spl mu/m silicon bipolar production technology with a cutoff frequency of 25 GHz. The circuit has a single-ended input and output and is mounted in a six-pin SOT363 plastic package.

SiGe HBTs and ICs for optical-fiber communication systems

An ultra-high-speed selective-epitaxial-growth (SEG) SiGe-base heterojunction bipolar transistor (HBT) with self-aligned stacked metal/in-situ doped poly-Si (IDP) (referred to as SMI) electrodes has been developed. A 0.54-μm-wide SiGe base self-aligned to the 0.14-μm-wide emitter, which reduces collector capacitance, was selectively grown by using a UHV/CVD system. SMI electrode technology, which enables low parasitic resistance, allows the intrinsic base profile to be kept shallow, so it is well suited to a SiGe-base HBT. A 2-μm-wide BPSG/SiO 2 refilled trench was introduced to reduce substrate capacitance by reducing its sidewall element. This makes it possible to obtain a 95-GHz cut-off frequency and ultra-high-speed emitter-coupled-logic (ECL) circuit with an 8.0-ps gate-delay. As applications for these SiGe HBTs, various ICs for optical-fiber-link systems have been developed. These include a 1/8 static frequency divider with a maximum operating frequency of up to 50 GHz, a time-division multiplexer and a demultiplexer operating at 40 Gb/s, a preamplifier with a bandwidth of 35 GHz, an AGC amplifier core with a bandwidth of 32 GHz, and a decision circuit operating at 40 Gb/s.

Transferred-substrate HBT integrated circuits

Using substrate transfer processes, we have fabricated heterojunction bipolar transistors with submicron emitter-base and collector-base junctions, minimizing RC parasitics and increasing f max to 500 GHz. The process also provides a microstrip wiring environment on a low- ϵ r dielectric substrate. Demonstrated small-scale ICs in the process include lumped and distribute amplifiers with bandwidths to 85 Hz, 48 GHz static frequency dividers, and 50GHz AGC/limiting amplifiers.

48-GHz digital ICs and 85-GHz baseband amplifiers using transferred-substrate HBT's

Using substrate transfer processes, we have fabricated heterojunction bipolar transistors with submicrometer emitter-base and collector-base junctions, minimizing RC parasitics and increasing f/sub max/ to 500 GHz. The process also provides a microstrip wiring environment on a low-/spl epsiv//sub r/ dielectric substrate. First design iterations of emitter-coupled-logic master-slave flip-flops exhibit 48 GHz maximum clock frequency when connected as static frequency dividers. Baseband amplifiers have been demonstrated with bandwidths up to 85 GHz.

48 GHz static frequency dividers in transferred-substrate HBT technology

In addition to an ultrahigh heterojunction bipolar transistor bandwidth, the transferred-substrate process offers the significant advantages of a low parasitic microstrip wiring environment and a low thermal impedance environment. The first digital integrated circuits using this technology, D-flipflops connected as 2:1 static frequency dividers, are reported.

20–40 Gbit/s GaAs-HEMT CHIP SET FOR OPTICAL DATA RECEIVER

Using our 0.2 and 0.3 μm AlGaAs/GaAs/AlGaAs quantum well HEMT technology, we have developed a chip set for 20–40 Gbit/s fiber-optical digital transmission systems. In this paper we describe nine analog and digital receiver ICs: a 22 GHz high-gain transimpedance amplifier, a 20 Gbit/s OEIC front-end optical receiver, a 25 Gbit/s automatic-gain-control amplifier, a limiting amplifier with a differential gain of 26 dB and a bandwidth of 27.7 GHz, a 20–40 Gbit/s clock recovery, a 20 Gbit/s low-power Master-Slave-D-Flipflop with 24 mW power dissipation, a parallel data decision and a 1:4 demultiplexer, both for bit rates of 40 Gbit/s, and a 30 GHz static frequency divider, respectively. All chips were characterized on wafers with 50 Ω coplanar test probes.

High-speed operation of static binary frequencydivider using resonanttunnelling diodes and HEMTs

A new circuit technology using resonant tunnelling diodes and HEMTs makes the toggle frequency f/sub toggle/ of a static binary frequency divider close to the cutoff frequency f/sub t/ of the used 0.7 /spl mu/m-gate HEMTs. f/sub toggle/ and f/sub t/ are 34 and 38 GHz, respectively. This technology is promising for use in high-speed logic circuits.

Very-high-speed InP/InGaAs HBT ICs for optical transmission systems

High-speed ICs for 20-40-Gbit/s time-division multiplexing (TDM) optical transmission systems have been designed and fabricated by using InP/InGaAs heterojunction-bipolar-transistor (HBT) technology. This paper describes four analog ICs and four digital ICs: a five-section cascode distributed amplifier with a gain of 9.5 dB and a bandwidth of 50 GHz, a three-section single-end-to-differential converter with a bandwidth of 40 GHz, a cascode differential amplifier with a gain of 10.5 dB and a bandwidth of 64 GHz, a preamplifier with a gain of 41.9 dB/spl Omega/ and a bandwidth of 39 GHz, a modulator driver with an output voltage swing of 3.2 V peak-to-peak and rise and fall times of 16 and 15 ps, a 40-Gbit/s selector, a 20-Gbit/s D-type flip-flop, and a static frequency divider with an operating range of 2.0-44.0 GHz. All the ICs were measured with on-wafer RF probes.

Over-60-GHz design technology for an SCFL dynamic frequency divider using InP-based HEMTs

A toggle operation of 39-63.5 GHz without tuning has been achieved by a digital dynamic frequency divider (DFD). The DFD employs a pair of clocked inverters (CIs) with source-coupled FET logic (SCFL) and uses 0.1-/spl mu/m-gate InAlAs/InGaAs/InP high electron-mobility transistors (HEMTs) of good uniformity and high performance. On a 2-in wafer, the frequency divider showed a maximum toggle frequency (f/sub tog,max/) of 59.1/spl plusmn/3.3 GHz and a fabrication yield of 89%. This is the highest operation frequency ever reported for a broad-band digital frequency divider. Comparison of the DFD and the static frequency divider (SFD) showed that the ratio of f/sub tog,max/ for the DFD to that for the SFD is much higher than the value expected from the linear-response theory. The comparison also showed that the ratio of the measured f/sub tog,max/ for the DFD to that for the SFD is 1.7, in contrast with the value of two expected from the circuit simulation. Delay-time analysis revealed that this 15% decrease of the ratio is due to the transmission delay of interconnections and charging time for stray capacitance.

Static frequency divider featuring reduced circuit complexity by utilizing resonant tunneling diodes in combination with HEMTs

A static frequency divider constructed with resonant tunneling diodes (RTDs) in combination with HEMTs is proposed and demonstrated. The circuit complexity is reduced drastically. The proposed circuit is fabricated using InP-based RTD/HEMT monolithic integration technology. Proper operation is demonstrated at room temperature by a quasi-static test pattern. The circuit includes two sub-circuits which behave like D-latches. Each sub-circuit consists of only three components. This number of components is one fifth of that required to construct a D-latch using conventional SCFL technology. The strong nonlinear I-V characteristics of RTD's are fully utilized for this reduction.

35-GHz static and 48-GHz dynamic frequency divider ICs using 0.2-/spl mu/m AlGaAs/GaAs-HEMTs

Two static and two dynamic frequency dividers based on enhancement and depletion 0.2-/spl mu/m gate length AlGaAs/GaAs-high electron mobility transistor (HEMT) (f/sub T/=60 and 55 GHz) technology were designed and fabricated. High-speed operations up to 35 GHz for the static frequency dividers and 48 GHz for the dynamic dividers, respectively, have been achieved. The single-ended input and differential outputs to ground simplify many applications. The power consumption is 250 mW for the divide-by-two dividers and 350 mW for the divide-by-four dividers using two supply voltages of 4 and -2.5 V.

Low power 20 Gbit/s data decision and 17 GHz staticfrequency divider ICs with 1.5 V supply voltage

A data decision and a static frequency divider in source coupled FET logic with a supply voltage of 1.5 V have been designed and fabricated. Both circuits, using 0.2 /spl mu/m gate length enhancement and depletion AlGaAs-GaAs HEMTs (f/sub T/=60/55 GHz), operate up to 20 Gbit/s and 17 GHz. The power consumption is 24 and 21 mW for the data decision circuit and the static frequency divider together with the output buffer, respectively.

46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider in silicon bipolar technology

High-speed multiplexers, demultiplexers, and static frequency dividers are key electronic components in future optical broadband communication systems. In this paper we present a 50 Gb/s multiplexer, a 46 Gb/s demultiplexer, and a 30 GHz static frequency divider. The IC's were fabricated in a self-aligning double-polysilicon bipolar technology using state-of-the-art production process modules. The achieved results are record speeds not only for silicon, but, except for the static divider, for all semiconductor technologies. The high performance of this chipset shows that circuits in silicon bipolar technology will play an important role in future multigigabit-per-second fiber-optic communication systems, at data rates of 20 Gb/s or even at 40 Gb/s.

High-yield design technologies for InAlAs/InGaAs/InP-HEMT analog-digital ICs

Sixty-GHz-band two-stage monolithic low-noise amplifiers and ultrahigh-speed SCFL static frequency dividers have been fabricated using the same InAlAs/InGaAs/InP HEMT process. This process assures uniformity by taking advantage of a 0.1-/spl mu/m T-shaped gate and an InP recess-etch stopper. Circuits are designed with priorities on stable operation, high yield, and uniformity. For the low-noise amplifier, the stabilization is optimized so as to minimize noise for the design gain while maintaining stability at all frequencies. The resultant amplifiers show a fabrication yield of 75% and at 62 GHz have a noise figure of 4.3/spl plusmn/0.19 dB and a gain of 11.8/spl plusmn/0.25 dB. For the frequency divider, the load resistance is set to be large enough to assure stable operation (circuit simulation shows that increasing the load resistance has little effect on the maximum toggle frequency). Frequency dividers designed with the optimum load resistance for stable and high-speed operation show a fabrication yield of 63% and have a maximum toggle frequency of 36.7/spl plusmn/0.55 GHz. These results demonstrate the feasibility of using this HEMT process to monolithically integrate analog and digital circuits on one chip.

A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's

This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage, which is 1/5 of the minimum value reported for D-FFs so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.

Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops

This paper presents two circuit techniques for highspeed operation of a master-slave toggle flip-flop circuit (MSTFF). One circuit reduces the gain in latching circuits, and the other uses the transient current of the emitter followers to boost the switching speed. Both the SPICE simulations and the measured results for static 1/8 frequency dividers fabricated using 0.5-/spl mu/m super self-aligned process technology (SSTIC) show that the maximum operating speed of our MS-TFF's is 10% and 30% faster than that of conventional ones. By applying these technologies, 19.1-GHz and 22.4-GHz Si bipolar static frequency dividers have been fabricated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>