Static Circuits Research Articles

Short Circuit Ruggedness of 600 V SiC Trench JFETs

Silicon Carbide JFETs with low on-state resistance are suitable for a number of high power applications. The static, dynamic and short circuit characterization of 600 V SiC Trench JFETs are reported in this paper. Typical JFETs fabricated with a 1.2 μm cell pitch had an on-resistance value around 40 mΩ and blocking voltages of ~600 V across the wafer. JFETs were successfully switched with a dc link voltage of 300 V, a current of 15 A and operating temperature of 125 °C. These JFETs were subjected to a short circuit condition with duration ranging from 10 μs to 45 μs at a dc link voltage of ~300 V, and operating temperatures of 25 °C and 125 °C. The device could withstand subsequent short circuit successfully without any failure at both 25 °C and 125 °C. The short circuit current showed consistent dependency on the applied gate voltage, when it was varied from 0 V to 15 V.

QSSTA: A Statistical Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits

Superconducting single flux quantum (SFQ) technology is an ultra-high performance and low power technology. The technology, however, lacks many of the design automation tools and capabilities that are commonplace in CMOS technology. This article describes methods to efficiently find the conditional probability density function (PDF) of the minimum workable clock period of SFQ circuits in view of manufacturing-induced process variations and presents qSSTA, a statistical static timing analysis tool targeting SFQ circuits. Following a grid-based correlation model, qSSTA represents spatial correlation of SFQ gates at different positions with respect to process parameters. By approximating timing characteristics of SFQ gates in a linear model, qSSTA is able to estimate the clock period as a normal random variable. Furthermore, process variations that generally result in extra delays in CMOS circuits can result in functional errors in SFQ circuits. qSSTA derives the closed form of the conditional PDF of the clock period under the scenario where all SFQ gates in the circuit work correctly. Compared to Monte Carlo simulations on look-up tables, experimental results show that the average percentage errors are 0.89% for the mean values, 8.04% for the standard deviation, and 0.61% for the 98-percentile point, whereas the runtime of qSSTA is 83% faster on average.

Optimizing the Performance of MOS Stacks

CMOS stack circuits find applications in multi-input exclusive-OR gates and barrel-shifters. Specifically, in wide fan-in CMOS NAND/NOR gates, the need arises to connect a relatively large number of NMOS/PMOS transistors in series in the pull-down network (PDN)/pull-up network (PUN). The resulting time delay is relatively high and the power consumption accordingly increases due to the need to deal with the various internal capacitances. The problem gets worse with increasing the number of inputs. In this paper, the performance of conventional static CMOS stack circuits is investigated quantitatively and a figure of merit expressing the performance is defined. The word “performance” includes the following three metrics; the average propagation delay, the power consumption, and the area. The optimum scaling factor corresponding to the best performance is determined. It is found that under the worst-case low-to-high transition at the output (that is, the input combination that results in the longest time delay in case of logic “1” at the output), there is an optimum value for the sizing of the PDN in order to minimize the average propagation delay. The proposed figure of merit is evaluated for different cases with the results discussed. The adopted models and the drawn conclusions are verified by comparison with simulation results adopting the 45 nm CMOS technology.

Clock delay-based design for hysteresis programming and noise reduction in dynamic comparators

Schmitt Triggers have found wide spread use in low-power and threshold-based applications such as peak detectors and spectrum analyzers. They are formed by comparators and feedback loops and exhibit hysteresis at nominal supply voltage. When using dynamic comparators, the periodic discharge of internal capacitors prior to each decision process cancels hysteresis. In addition, dynamic comparators produce considerable noise that may affect the operation of hysteresis-based applications. Therefore, currently, Schmitt Triggers are mainly designed as static circuits at the price of less operation speed, more silicon area and higher power consumption compared to their analog counterparts. This paper presents a new low-noise dynamic comparator with programmable hysteresis. Using an advanced comparator structure, as the two-stage dual-clock latch comparator, the hysteresis could be adjusted over more than 30 mV by programming the delay between the two clocks. Moreover, the same delay has been used to reduce the switching noise. The peak kickback noise is then reduced by more than 70%. This has been achieved by designing a customized 4-bit programmable delay circuit. Although several functionalities have been added to the circuit, the proposed design include only a few extra elements with respect to the basic one. As a result, the total consumed energy at 500 MHz is 1.2 pJ/decision only, while the static power consumption is less than 65 pW.

CMBF-based dynamic selection for heterogeneous massive MIMO systems

In this paper, an optimal coordinated multipoint beamforming (CMBF) scheme is proposed for heterogeneous networks (HetNets) with massive multiple input multiple output (MIMO) systems for energy efficiency (EE), taking into account the maximum transmission power of the base station (BS) with the limitation on the power consumption of the static circuit. This paper analyzes the influence of the different parameters on the EE and derives a closed-form expression. We investigate the different cooperation schemes, considering the influence of the number of antennas of small base station (SBS) and macro base station (MBS), the quality of service (QoS), and the number of different service users. Therefore, the best parameters can be selected for optimizing EE with the different scenarios in HetNets with massive MIMO systems. Theoretical derivation and simulations show that the amount of BS antennas, achievable rate constraints, quantity of service users, and cooperative schemes all have the vital influences on the EE for the CMBF design. Therefore, the proposed optimization framework enables us to identify key system parameters, and obtain the better system design for the massive MIMO HetNets.

Facilitating Conceptual Changes of High School Students regarding Concepts in Static Electricity and DC Circuits through the Use of VMSCDCCText

The purpose of this study was to find out the effectivity of using visual multimedia supported-conceptual development conceptual change text (VMS-CDCCText) in facilitating conceptual change of high school students related to the concepts in Static Electricity and DC Circuits subject matter. VMS-CDCCText consists of seven parts of the text. The method used in this study is a pre-experiment with one group pretest-posttest design. The number of research subjects was 80 students consisting of 46 female and 34 male students, at one high schools in West Java province Indonesia. Data about the state of students' conceptions were collected by conception test in the four tier test format. The results showed that the number of students who reached the type of construction and reconstruction on the two concept labels covered in the Static Electricity and two concept labels covered in the DC Circuits subject matter was above 70%. These results indicate that the use of VMS-CDCCText has a high effectiveness in facilitating the attainment of conceptual changes in construction and reconstruction types that lead to ownership of scientific conceptions.

Throughput Maximization for UAV-Aided Backscatter Communication Networks

This paper investigates unmanned aerial vehicle (UAV)-aided backscatter communication (BackCom) networks, where the UAV is leveraged to help the backscatter device (BD) forward signals to the receiver. Based on the presence or absence of a direct link between BD and receiver, two protocols, namely transmit-backscatter (TB) protocol and transmit-backscatter-relay (TBR) protocol, are proposed to utilize the UAV to assist the BD. In particular, we formulate the system throughput maximization problems for the two protocols by jointly optimizing the time allocation, reflection coefficient and UAV trajectory. Different static/dynamic circuit power consumption models for the two protocols are analyzed. The resulting optimization problems are shown to be non-convex, which are challenging to solve. We first consider the dynamic circuit power consumption model, and decompose the original problems into three sub-problems, namely time allocation optimization with fixed UAV trajectory and reflection coefficient, reflection coefficient optimization with fixed UAV trajectory and time allocation, and UAV trajectory optimization with fixed reflection coefficient and time allocation. Then, an efficient iterative algorithm is proposed for both protocols by leveraging the block coordinate descent method and successive convex approximation (SCA) techniques. In addition, for the static circuit power consumption model, we obtain the optimal time allocation with a given reflection coefficient and UAV trajectory and the optimal reflection coefficient with low computational complexity by using the Lagrangian dual method. Simulation results show that the proposed protocols are able to achieve significant throughput gains over the compared benchmarks.

Different Types of Ultra-low Power Energy-Harvesting Design Techniques for IoT Applications

In this paper, different type of level shifter circuits, that can able to convert the sub-threshold level to super-threshold level signals are discussed. To develop the ultra- low static power consumption circuit designs such a way to switch on the transistor for a low voltage levels. To enhance the switching speed and minimize the dynamic power consumption, by incorporating the CMOS –inverter buffer circuit at the output side to improve the energy efficiently. These energy harvesting design techniques provides endless energy supply to electronic systems that are remotely located areas. More number of devices are controlled by IoT (Internet of Things) to perform the operation by remote sensing.

Different Types of Ultra-low Power Energy-Harvesting Design Techniques for IoT Applications

In this paper, different type of level shifter circuits, that can able to convert the sub-threshold level to superthreshold level signals are discussed. To develop the ultra- low static power consumption circuit designs such a way to switch on the transistor for a low voltage levels. To enhance the switching speed and minimize the dynamic power consumption, by incorporating the CMOS –inverter buffer circuit at the output side to improve the energy efficiently. These energy harvesting design techniques provides endless energy supply to electronic systems that are remotely located areas. More number of devices are controlled by IoT (Internet of Things) to perform the operation by remote sensing.

Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

An Introduction to IEEE Standard 1458-2017: Recommended Practice Update for Molded-Case Circuit Breakers for Industrial Applications

IEEE standard 1458-2017 is an updated recommended practice (RP) that provides in one document the information necessary to select, apply, and maintain (determine the remaining life of) molded-case circuit breakers. The document provides information on the basics of circuit breaker design and presents a detailed procedure to determine when molded-case circuit breakers must be replaced. Informative annexes introduce guidelines on the reuse of low-voltage circuit breakers, the use of moldedcase circuit breakers for dc voltage and frequencies greater than 60 Hz, and static converter feeder circuit breaker applications [1].

Design of Manchester Carry Chain Adder using High speed Domino Logic

Dynamic logic circuits are preferred over static logic circuits for their increased speed performance and lower power consumption. However, they are found prone to false evaluation while cascading multiple stages of dynamic logic circuits. To overcome this problem, the domino logic circuits were proposed by researchers. However, they offer reduced noise margins due to increased leakage current and charge sharing problems. In this paper, Manchester Carry Chain Adder design is explored for use with domino logic and comparison of various domino logic topologies intended for improved noise immunity and reduced leakage current against the proposed structure have been carried out. Wide fan-in gates and 8-bit Manchester Carry Chain Adder (MCC) based on various high speed domino logic circuit topologies have been designed using Cadence® using 180nm technology library from TSMC. Design of 8-bit OR gate, using High Speed Domino (HSD) topology consumes 10.8% lower power in comparison with Controlled-Current Comparison-based domino logic (C3D) topology. Furthermore, it is observed that an 8-bit Manchester Carry Chain adder using HSD topology is 5.027 times faster than C3D topology and the leakage power consumption is also reduced.

Computational and Experimental Simulation of Static Memory Cells of Submicron Microcircuits under the Effect of Neutron Fluxes

The simulation of reversible single events in test samples of static memory microcircuits with design norms of 0.5, 0.35, 0.25, and 0.1 μm under the effect of neutron fluxes with various energies is performed. It is shown theoretically and experimentally that reversible single events can occur in modern microelectronics and nanoelectronics products under the effect of a fission-spectrum neutron flux caused by the passage of primary recoil atoms and nuclear reaction products along the microcircuit surface perpendicularly to the electric current lines in the near-drain transistor area. A series of irradiation experiments of static memory circuits with design norms of 0.35 μm is interpreted based on the proposed model.

Experimental investigation of torque measurement in hermetic compressor

In order to measure the compressor torque accurately and guide the design efficiently, a torque measurement method for the hermetic compressor is proposed. Then the shaft power measuring system is established by using a virtual instrument developed by LabVIEW. The stability of slip ring is monitored in real time through an external static full bridge circuit for eliminating the influence of its unstable contact resistance on measurement during the working process. The experimental results indicate that the change of contact resistance cannot be neglected in measuring process. The experimental torque curve is in agreement with the theoretical one. The measured shaft power of the prototype is 320W, finally the motor efficiency and the mechanical efficiency is 91.7% and 89.1%, respectively.

Electrical Stability Analysis of Dynamic Logic Using Amorphous Indium–Gallium–Zinc-Oxide TFTs

Prior research has reported that the device characteristics of amorphous indium–gallium–zinc-oxide (a-IGZO) thin-film transistors (TFTs) have been changed by instabilities due to electrical stress. Because positive bias stress and high current stress produce a positive threshold voltage shift, if the digital logic circuit is designed using a-IGZO TFTs, there is a high possibility that the circuit suffers from malfunction. In this letter, the dynamic and the static logic circuits using n-type a-IGZO TFTs are compared in terms of stability for electrical stress. In order to compare the stability of the two circuits, DC and AC signals are applied. The measurement results suggest that the dynamic logic circuit is much more stable than the static logic circuit regarding electrical stress.

Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems

Based on the relationship between circuits (systems) and the signals in the circuits (systems), the theory of expansion Boolean algebra is presented in this paper. Static complementary logic circuits and static pass transistors logic circuits have been used to implement the high-speed and low-power-consumption cells circuits in CMOS VLSI systems. It is important to study the extraction method of logic expressions for these types of circuits. By analyzing the operations principles of MOS transistors in CMOS circuits, the theory of expansion Boolean algebra of CMOS logical circuits is presented. Based on the algebraic theory, a method of extracting the logic expressions from the two types of CMOS logical circuits is derived. On the basis of the method, a switch-level design method of CMOS logic circuits based on the algebra theory is presented, and the design method is used to design the high-speed and low-power full adder cells in CMOS VLSI systems. By the results of the simulation experiments, it is shown that the pass transistors and transmission gates hybrid CMOS full adder circuits proposed in this paper have a lower power-delay product by comparison with the full adder circuits designed by using other methods.

Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> -dependence of threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> .

Secrecy Energy Efficiency Optimization for Downlink Two-User OFDMA Networks With SWIPT

Simultaneous wireless information and power transfer (SWIPT), as a promising technology by which mobile devices are designed by both information decoding and energy harvesting at the same time, has recently drawn significant interests. However, in multiuser scenario, a challenging physical layer security issue arises as the confident messages sent to the intended information receivers may be eavesdropped by other receivers. To address this problem, in this paper, secrecy energy efficiency maximization (SEEM) problem is investigated for two-user orthogonal frequency-division multiple access networks with SWIPT. Specifically, a power splitting scheme is adopted for each user, which would split received radio frequency signals into two independent parts for information decoding and energy harvesting, respectively. Taking both the individual secrecy quality of service requirement and the individual harvested energy constraint into consideration, the SEEM problem is formulated as a nonlinear fractional programming problem. Moreover, according to Dinkelbach's method, a power allocation and power splitting (PAPS) algorithm is proposed by solving the equivalent convex optimization problem. Finally, numerical results verify the impact of static circuit power consumption, maximum transmit power, power split ratio, subcarrier bandwidth, and path loss on secrecy energy efficiency of our PAPS algorithm.

On-Chip Static Phase Difference Measurement Circuit With Gain and Offset Calibration

A gain and offset-calibrated 3-state phase detector is proposed to accurately measure static phase difference. Forcing the phase detector to operate in two different modes provides the full-scalegain since the sum of the two results is ${2}{\pi }$ . Flipping the inputs and averaging the results cancels the offset. Proposed circuit enhancements realize a robust reset and a gain, independent of waveform rise/fall times. A $0.13-\boldsymbol {\mu }\text{m}$ CMOS prototype of the proposed enhanced phase detector has errors ≤ 0.5° for 2.4-GHz quadrature inputs. It consumes 3.6mA from 1.2V and occupies 0.0416 mm2. The proposed circuit can be used for on-chip measurement and calibration of multi-phase clock generators in radios and clocking circuits.

Microwave analysis of SiGe heterojunction double‐gate tunneling field‐effect transistor through its small‐signal equivalent circuit

In this study, Si0.5Ge0.5 was used as a source junction material in a tunneling field-effect transistor (TFET), which was analyzed using technology computer-aided design (TCAD) simulation and a small-signal non-quasi static (NQS) equivalent circuit. The NQS equivalent circuit with additional tunneling resistance (Rtunnel) enables more accurate analyses. By using a de-embedding process, small-signal parameters in the intrinsic area were obtained. This process was used to analyze the resistance and capacitance in each section, the tendencies of the materials, and the voltage. The error between the NQS equivalent circuit and TCAD device simulation was within 1.9% in the 400-GHz regime. A cut-off frequency (fT) of up to 0.876 GHz and maximum oscillation frequency (fmax) of 146 GHz were obtained.