Start-up Circuit Research Articles

A sine-LO square-law harmonic-rejection mixer—theory, implementation, and application

A square-law harmonic-rejection mixer (SL-HRM) driven by a sine local oscillator (LO) is proposed for wideband and tunable rejection of all LO harmonics. The key performances including the gain, noise figure (NF), input-referred third-order intercept point (IIP3), and harmonic rejection ratio (HRR) with respect to the amplitude and purity of the sine-LO are analyzed. In the circuit level, the SL-HRM incorporates a voltage-boosted technique to surmount the gain and NF penalties of square-law mixing, while guaranteeing the device reliability via introducing a supply startup circuit and a node-voltage protection circuit. The entailed high-purity sine-LO is achieved via a digital-intensive square-to-sine LO generator plus a passive- RC low-pass filter. Fabricated in 65-nm CMOS, the VHF-/UHF-band SL-HRM has a tunable gain of 1-13 dB, associated with an NF of 27-15 dB, under an LO amplitude of 50-200 mV pp. The IIP3 is stable within from +6.5 to +7.6 dBm, as expected. The tunable HRR3 and HRR5 are 13-40 dB and 17-45 dB, respectively. The mixer core consumes 7.5 mW at 2.5 V, while the LO generator draws 3-6 mW at 1.2 V. The total active area is just 0.042 mm2.

Minimal power start-up circuit design for self-biased CMOS current generators

A new start-up circuit configuration, with minimal standby power dissipation, is proposed for CMOS self-biased current generators. Using standard 0.13 µm CMOS technology, simulation results show that for a supply voltage range 1.8 V to 2.5 V and a temperature range −40°C to +85°C, the circuit standby power dissipation is less than 20 nW.

Experience gained from mastering the operation of the Kirishi district power station unit 6 modernized using the combined-cycle technology

This article is devoted to the retrofitting of one of the 300-MW power units at the Kirishi district power station carried out using the combined-cycle technology in order to increase the power unit capacity and make it more efficient. The main and auxiliary equipment of the retrofitted power unit are described. The problems revealed and solved in the course of adjustment works are mentioned. Problems concerned with organizing the startup modes of combined-cycle power units fitted with three-loop heat-recovery boilers and a double-bypass startup circuit arrangement are touched. The design and actually achieved technical and economic indicators of the main equipment and the power unit as a whole are presented. A tangible economic effect is noted from a comparison of the key indicators before and after the retrofitting. It is shown that the retrofitted power unit has good environmental indicators and a very high level of automation.

Design of RF energy harvesting platforms for power management unit with start-up circuits

In this contribution we discuss an unconventional rectifier design dedicated to RF energy harvesting from ultra-low sources, such as ambient RF sources which are typically of the order of few to few tens of μW. In such conditions unsuccessful results may occur if the rectenna is directly connected to its actual load since either the minimum power or the minimum activation voltage may not be simultaneously available. For this reason a double-branch rectifier topology is considered for the power management unit (PMU), instead of traditional single-branch one. The new PMU, interposed between the rectenna and application circuits, allows the system to operate with significantly lower input power with respect to the traditional solution, while preserving efficiency during steady-state power conversion.

Low‐cost low‐power HV startup circuit with 50 V pJFET and 700 V T‐nJFET

An advanced low-cost and low-power high-voltage (HV) startup circuit which uses a 50 V pJFET and a 700 V T-nJFET (triple RESURF nJFET) is proposed. Compared with traditional technology, a mass of module area is saved. This mainly benefits from: first, with increase of V DS, I OFF (leakage current in off-state) can be quickly pinched off to a low value by pJFET without a large layout area which is needed for the traditional resistance method. Secondly, T-nJFET is located at the drain terminal of T-nLDMOS (triple RESURF LDMOS) with common drain electrode which also saves large area than traditional independent nJFET. Moreover, pJFET brings stable and low I OFF which leads to 4 mW P OFF (static power consumption in off-state) due to its low V P (pinch-off voltage) and high BVDS.

A Novel BiCMOS Current-Mode Bandgap Reference

In this paper, a novel BiCMOS current steering bandgap is presented, which includes reference core, start-up circuit, and output circuit, of which the reference core is used to produce the temperature-stable current, the start-up to start up the reference core when powered on, and the output circuit to proportionally transport the reference current to other cells on the same chip. Compared to the traditional voltage-mode bandgap reference, because of the adoption of the current-steering mode, the reference proposed in this paper, has the merits of being immune to variation of the power supply, minimum transport consumption, better matches, temperature stability, smaller area, auto-startup, and so on, which are specially needed in AD/DA application. The simulation shows that the proposed current-mode reference circuit has full temperature range coefficient of 8.9ppm, which is better than that of the traditional voltage-and current-mode reference circuits.

Design and Implementation of Op-Amp Based Low-Power CMOS Bandgap Voltage Reference with Minimum Supply oF 0.8-V

A low power voltage source is generated by altering the device size in existing topology has been presented. Bandgap voltage reference is generated by combination of start-up, supply independent, operational amplifier (Op-amp) and bandgap core circuits which has been designed such that low sensitivity of temperature and supply variation. It has been designed with minimum supply of 0.8 V without use of low threshold device, and the maximum supply current is 35 µA. It has been implemented in 180 nm standard digital CMOS Process. The circuit generates a reference voltage of 540 mV and has a temperature coefficient of 14 ppm /°C from −40 °C to 120 °C. The generated reference voltage is independent of temperature and supply variations have been mathematically proved by analyzing the circuit design. Also, proper selection of on-chip passive components and its values has been chosen which is based on low noise. Comparing the pre and post layout simulation results has been presented.

A High Frequency Active Voltage Doubler in Standard CMOS Using Offset-Controlled Comparators for Inductive Power Transmission

In this paper, we present a fully integrated active voltage doubler in CMOS technology using offset-controlled high speed comparators for extending the range of inductive power transmission to implantable microelectronic devices (IMD) and radio-frequency identification (RFID) tags. This active voltage doubler provides considerably higher power conversion efficiency (PCE) and lower dropout voltage compared to its passive counterpart and requires lower input voltage than active rectifiers, leading to reliable and efficient operation with weakly coupled inductive links. The offset-controlled functions in the comparators compensate for turn-on and turn-off delays to not only maximize the forward charging current to the load but also minimize the back current, optimizing PCE in the high frequency (HF) band. We fabricated the active voltage doubler in a 0.5-μm 3M2P std . CMOS process, occupying 0.144 mm(2) of chip area. With 1.46 V peak AC input at 13.56 MHz, the active voltage doubler provides 2.4 V DC output across a 1 kΩ load, achieving the highest PCE = 79% ever reported at this frequency. In addition, the built-in start-up circuit ensures a reliable operation at lower voltages.

Start‐up circuit for low‐power indoor light energy harvesting applications

A start-up circuit, used in a micro-power indoor light energy harvesting system, is described. This start-up circuit achieves two goals: first, to produce a reset signal, power-on-reset (POR), for the energy harvesting system, and secondly, to temporarily shunt the output of the photovoltaic (PV) cells, to the output node of the system, which is connected to a capacitor. This capacitor is charged to a suitable value, so that a voltage step-up converter starts operating, thus increasing the output voltage to a larger value than the one provided by the PV cells. A prototype of the circuit was manufactured in a 130 nm CMOS technology, occupying an area of only 0.019 mm2. Experimental results demonstrate the correct operation of the circuit, being able to correctly start-up the system, even when having an input as low as 390 mV using, in this case, an estimated energy of only 5.3 pJ to produce the start-up.

Design, Fabrication and Testing of Two Different Laboratory Prototypes of CSI-based Induction Heating Units

Induction heating is a non-contact heating process which became popular due to its energy efficiency. Current source inverter (CSI) based induction heating units are commonly used in the industry. Most of these CSIs are thyristor based, since thyristors of higher ratings are easily available. These being load commutated apparatus a start-up circuit is needed to initiate commutation. In this paper the design and fabrication of two laboratory prototypes have been presented. The first one, a SCR-based CSI fed controlled induction heating unit (IHU), has been tested with two different types of start-up procedures. Thereafter the fabrication and performance of another IGBT-based CSI is compared with the thyristor-based CSI for a 2 kW, 10 kHz application. These two types of CSIs are fully fabricated in laboratory along with the IHU. Performance analysis and simulation of two different CSIs has been done by using SequelGUI2. The triggering pulses for the inverter devices (for both CSI devices as well as auxilliary thyristor of start-up circuit) have been generated and closed-loop control has been done in FPGA platform built around an Altera make cyclone EPIC12Q240C processor which can be programmed using Quartus II software. Close agreement between simulated and experimental results highlight the accuracy of the experimental work.

The PreAmplifier ShAper for the ALICE TPC detector

In this paper the PreAmplifier ShAper (PASA) for the Time Projection Chamber (TPC) of the ALICE experiment at LHC is presented. The ALICE TPC PASA is an ASIC that integrates 16 identical channels, each consisting of Charge Sensitive Amplifiers (CSA) followed by a Pole-Zero network, self-adaptive bias network, two second-order bridged-T filters, two non-inverting level shifters and a start-up circuit. The circuit is optimized for a detector capacitance of 18–25pF. For an input capacitance of 25pF, the PASA features a conversion gain of 12.74mV/fC, a peaking time of 160ns, a FWHM of 190ns, a power consumption of 11.65mW/ch and an equivalent noise charge of 244e+17e/pF. The circuit recovers smoothly to the baseline in about 600ns. An integral non-linearity of 0.19% with an output swing of about 2.1V is also achieved. The total area of the chip is 18mm2 and is implemented in AMS's C35B3C1 0.35μm CMOS technology. Detailed characterization tests were performed on about 48000 PASA circuits before mounting them on the ALICE TPC front-end cards. After more than two years of operation of the ALICE TPC with p–p and Pb–Pb collisions, the PASA has demonstrated to fulfill all requirements.

Startup Circuit Training Program Reduces Metabolic Risk in Latino Adolescents

Startup Circuit Training Program Reduces Metabolic Risk in Latino Adolescents

Startup Circuit Training Program Reduces Metabolic Risk in Latino Adolescents

This study aimed to test the effects of a circuit training (CT; aerobic + strength training) program, with and without motivational interviewing (MI) behavioral therapy, on reducing adiposity and type 2 diabetes risk factors in Latina teenagers. Thirty-eight Latina adolescents (15.8 ± 1.1 yr) who are overweight/obese were randomly assigned to control (C; n = 12), CT (n = 14), or CT + MI (n = 12). The CT classes were held twice a week (60-90 min) for 16 wk. The CT + MI group also received individual or group MI sessions every other week. The following were measured before and after intervention: strength by one-repetition maximum; cardiorespiratory fitness (V·O 2max) by submaximal treadmill test; physical activity by accelerometry; dietary intake by records; height, weight, waist circumference; total body composition by dual-energy x-ray absorptiometry; visceral adipose tissue, subcutaneous adipose tissue, and hepatic fat fraction by magnetic resonance imaging; and glucose/insulin indices by fasting blood draw. Across-intervention group effects were tested using repeated-measures ANOVA with post hoc pairwise comparisons. CT and CT + MI participants, compared with controls, significantly increased fitness (+16% and +15% vs -6%, P = 0.03) and leg press (+40% vs +20%, P = 0.007). Compared with controls, CT participants also decreased waist circumference (-3% vs +3%; P < 0.001), subcutaneous adipose tissue (-10% vs 8%, P = 0.04), visceral adipose tissue (-10% vs +6%, P = 0.05), fasting insulin (-24% vs +6%, P = 0.03), and insulin resistance (-21% vs -4%, P = 0.05). CT may be an effective starter program to reduce fat depots and improve insulin resistance in Latino youth who are overweight/obese, whereas the additional MI therapy showed no additive effect on these health outcomes.

Start-up circuit with low minimum operating power for microwatt energy harvesters

Remote sensors powered by energy harvesting need to restart successfully after long periods of no available energy, during which all stored energy may have been depleted. This start-up is affected by known phenomena such as ‘lock-up’ and ‘voltage collapse’. In this study, the authors address these phenomena in the context of energy harvesting where the energy required for a sense and transmit cycle is accumulated over long time periods at low power. A voltage-detecting switch with very low power consumption is proposed, which avoids system lock-up. This start-up circuit uses an array of discrete MOSFETs operated in their sub-threshold regions. A performance metric for start-up circuits is proposed. ‘Minimum operating power’ is the harvester power level below which the load does not start up. Reducing this minimum operating power thus reduces the required size of harvester or increases the application range. For the proposed circuit, a minimum operating power of 3.5 µW is derived experimentally, and recommendations are provided to further reduce this. The minimum operating power of the proposed circuit is shown to be a strong function of capacitive surge current, and surge current associated with undefined logic states. The transient contribution of components to the quiescent power is analysed through experiment. Simulation shows that increased temperature not only reduces the minimum operating power, but also reduces the energy available to the load.

낮은 변압기 턴비를 갖는 고승압.대전력용 3상 ZVS DC-DC컨버터

제안하는 컨버터는 부스트 하프브리지-전압 더블러를 각각 병렬-직렬로 연결하여 출력전력 및 출력전압을 증대시키므로 고승압 대전력 응용에서 소자의 선정이 용이하다. 특히 고주파변압기 턴 비를 작게 할 수 있고 DC 오프셋이 제거되어 최적의 변압기 설계가 가능하며, 3개의 코아로 전력이 분배되어 Low Profile 및 열 분산에 유리하다. 제안하는 컨버터는 전 영역(0 ∼ 1)의 듀티 사용으로 스타트업 및 추가의 클램프회로가 필요 없으며 입력전압 변동이 큰 응용에 적합하다. 또한 넓은 듀티영역에서 스위치의 ZVS 턴온과 다이오드의 ZCS 턴온 턴오프가 성취되므로 고효율을 달성할 수 있다. 제안하는 컨버터를 5 kW급 시작품으로 검증하였다. The proposed converter has easy device selection for high step-up and high power applications since boost half bridge and voltage doubler cells are connected, respectively, in parallel and series in order to increase output power and voltage. Especially, optimized design of high frequency transformers is possible owing to reduced turn ratio and eliminated dc offset, and distributed power through three cores is beneficial to low profile and thermal distribution. The proposed converter does not necessitate start-up circuit and additional clamp circuit due to the use of whole duty range between 0 and 1 and is suitable for applications with wide input voltage range. Also, high efficiency can be achieved since ZVS turn on of switches are achieved in wide duty cycle range and ZCS turn on and off of diodes are achieved. The proposed converter was validated through 5 kW prototype.

Design and Implementation of a Direct AC–DC Boost Converter for Low-Voltage Energy Harvesting

In this paper, a direct ac-dc power electronic converter topology is proposed for efficient and optimum energy harvesting from low-voltage microgenerators. The converter utilizes the bidirectional current-conduction capability of MOSFETs to avoid the use of a front-end bridge rectifier. It is operated in discontinuous conduction mode and offers a resistive load to the microgenerator. Detailed analysis and modeling of the converter is presented. In such low-power applications, the power consumption of gate drive and control circuits should be minimal. In this paper, they are specifically designed to consume very low power. A suitable startup circuit and auxiliary dc supply circuit is proposed for the implementation of the converter. A low-voltage microgenerator is used to verify the performance and operation of the converter and the gate drive circuits.

Multiphase DC–DC Converters Using a Boost-Half-Bridge Cell for High-Voltage and High-Power Applications

In this paper, multiphase dc-dc converters are proposed for high-voltage and high-power applications. A generalized converter is configured such that the boost-half-bridge (BHB) cells and voltage doublers are connected in parallel or in series to increase the output voltage and/or the output power. In addition to reduced device voltage and current ratings by the connection, the proposed converter has the following features: high-step-up voltage gain with significantly reduced transformer turn ratio, low-input current ripple due to interleaving effect, zero-voltage switching turn-ON of switches and zero-current switching turn-OFF of diodes, no additional clamping and start-up circuits required, high-component availability and easy thermal distribution due to the use of multiple small components, and flexibility in device selection resulting in optimized design. A design guideline of determining the optimum circuit configuration for given output voltage and power level is presented. Experimental results are also provided to validate the proposed concept.

A 120mV startup circuit based on charge pump for energy harvesting circuits

In this paper, a 120mV input startup circuit based on novel charge pump architecture is proposed. The startup circuit can boost input voltages ranging from 120mV to 300mV while supplying voltages 280mV to 1.6V at the output with approximately 23% efficiency. To verify the circuit behavior, the test circuit has been implemented using 0.18µm CMOS process. The low voltage, low area startup circuit is suitable for ultra low voltage applications such as energy harvesters and allows for single chip integration.

A Resistor-Compensation Technique for CMOS Bandgap and Current Reference with Simplified Start-Up Circuit

This paper presents a resistor-compensation technique for a CMOS bandgap and current reference, which utilizes various high positive temperature coefficient (TC) resistors, a two-stage operational transconductance amplifier (OTA) and a simplified start-up circuit in the 0.35-µm CMOS process. In the proposed bandgap and current reference, numerous compensated resistors, which have a high positive temperature coefficient (TC), are added to the parasitic n-p-n and p-n-p bipolar junction transistor devices, to generate a temperature-independent voltage reference and current reference. The measurements verify a current reference of 735.6nA, the voltage reference of 888.1mV, and the power consumption of 91.28µW at a supply voltage of 3.3V. The voltage TC is 49ppm/°C in the temperature range from 0°C to 100°C and 12.8ppm/°C from 30°C to 100°C. The current TC is 119.2ppm/°C at temperatures of 0°C to 100°C. Measurement results also demonstrate a stable voltage reference at high temperature (> 30°C), and a constant current reference at low temperature (< 70°C).

A Battery-Less Thermoelectric Energy Harvesting Interface Circuit With 35 mV Startup Voltage

A battery-less thermoelectric energy harvesting interface circuit to extract electrical energy from human body heat is implemented in a 0.35 CMOS process. A mechanically assisted startup circuit enables operation of the system from input voltages as low as 35 mV. An efficient control circuit that performs maximal transfer of the extracted energy to a storage capacitor and regulates the output voltage at 1.8 V is presented.