Standard IC Process Research Articles

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Substrate transfer for RF technologies

The constant pressure on performance improvement in RF processes is aimed at higher frequencies, less power consumption, and a higher integration level of high quality passives with digital active devices. Although excellent for the fabrication of active devices, it is the silicon substrate as a carrier that is blocking breakthroughs. Since all devices on a silicon wafer have a capacitive coupling to the resistive substrate, this results in a dissipation of RF energy, poor quality passives, cross-talk, and injection of thermal noise. We have developed a low-cost wafer-scale post-processing technology for transferring circuits, fabricated with standard IC processing, to an alternative substrate, e.g., glass. This technique comprises the gluing of a fully processed wafer, top down, to an alternative carrier followed by either partial or complete removal of the original silicon substrate. This effectively removes the drawbacks of silicon as a circuit carrier and enables the integration of high-quality passive components and eliminates cross-talk between circuit parts. A considerable development effort has brought this technology to a production-ready level of maturity. Batch-to-batch production equipment is now available and the technology and know-how are being licensed. In this paper, we present four examples to demonstrate the versatility of substrate transfer for RF applications.

Release of multi-layer metal structure in MEMS devices by dry etching technique

Reactive ion etching technique was used to remove interleave photoresist layer for free standing metal structure in microelectromechanical systems (MEMS) devices. Mixture of oxygen and CF 4 gas was used to get isotropic etching profile. Etching process was optimized to get large metal structure of 100×100 μm 2 without any surface bending. The etching rate of 0.7 μm/min at 60 W of RIE plasma power is found to be optimum process for the particular application. The reported dry release technique is fully compatible with standard silicon IC processing and hence can be used for hybridize process used in MEMS array application.

A micromachined RF low phase noise voltage-controlled oscillator for wireless communications

An RF low phase noise voltage-controlled oscillator is implemented with micromachined IC-compatible variable capacitors and three-dimensional coil inductor. Unlike conventional on-chip passive devices, the micromachined variable capacitors achieve a high-Q value above 60 at 1 GHz with a 15% tuning range for a nominal 2 pF capacitance with 3 V tuning voltage. Three-dimensional inductors minimize the substrate loss and achieve a Q of 30 at 1 GHz with a 4.8 nH inductance. Both passive components are fabricated on silicon substrates and thus amenable to monolithic integration with standard IC process. The prototype VCO exhibits −136 dBc/Hz phase noise at 3 MHz offset frequency from the carrier, suitable for most wireless communication applications, in particular GSM. The VCO is tunable from 855 Mhz to 863 MHz, limited by the test set-up. © 2001 John Wiley & Sons, Inc. Int J RF and Microwave CAE 11: 285–300, 2001.

Infrared micro-spectrometer based on a diffraction grating

The optical properties of crystalline silicon in the IR spectral range have been used for the realisation of a grating type micro-spectrometer. An aluminium metallisation on a double side polished silicon wafer is used for fabrication of the multi-slit gratings. The dispersed spectrum propagates through this silicon wafer and is projected on an array of polysilicon thermopiles, integrated in a second bulk micromachined silicon wafer. The two wafers are bonded at low temperature. An IR spectrometer results, which is simple to fabricate and remains compatible with standard IC processing.

A novel SnO 2/Al discrete gate ISFET pH sensor with CMOS standard process

In this paper, we present a method allowing industrial production of integrated ion sensitive field effect transistor (ISFET) sensor. An ASIC CMOS standard process is used to integrate the sensor and signal processing circuit; then the sensor is plated with the sensing membrane (SnO 2) by sputtering. The structure of the ISFET is novel SnO 2/Al discrete gate. The discrete gate ISFET and the readout circuit were fabricated with a conventional standard CMOS IC process where no extra mask was required. The experimental data show that the SnO 2/Al discrete gate ISFET sensors have a high linearity of 58 mV/pH in a concentration ranging from pH 2 to 10. The low offset and low power readout circuit for the discrete gate ISFETs pH sensor was designed and evaluated for monolithic in this study.

Single level integrated packaging modules for high performance electronic systems

In this paper, we studied a novel packaging scenario that aims to integrate or eliminate the existing multilevel packaging hierarchies toward single level integration. This new approach is an extension of VLSI technology where standard IC processes were pursued in the whole fabrication sequence. Main benefits include very high performance, ultra high density, mixed-signal integration, and inexpensive. Several key technologies such as chip assembly and planarization were developed. A feasible fabrication procedure for single level integration has been established. Demonstrating modules were presented. Interconnect structures, signal and power distribution, and electrical performance were studied theoretically and experimentally for GHz off-chip operating. Properties of signal propagation and coupling from chip to chip were investigated both in frequency domain and in time domain by simulations and by high frequency measurements. The studies show that the new modules are capable of several Gb/s/pin data rate for off-chip communications. Besides, some design guidelines for best performance are obtained through the work.

An integrated CMOS microluminometer for low-level luminescence sensing in the bioluminescent bioreporter integrated circuit

We report an integrated CMOS microluminometer for the detection of low-level bioluminescence in whole cell biosensing applications. This microluminometer is the microelectronic portion of the bioluminescent bioreporter integrated circuit (BBIC). This device uses the n-well/p-substrate junction of a standard bulk CMOS IC process to form the integrated photodetector. This photodetector uses a distributed electrode configuration that minimizes detector noise. Signal processing is accomplished with a current-to-frequency converter circuit that forms the causal portion of the matched filter for dc luminescence in wide-band white noise. Measurements show that luminescence can be detected from as few as 4×10 5 cells/ml.

The determination of the elastic modulus of microcantilever beams using atomic force microscopy

An investigation into the determination of the micromechanical properties of thin film materials has been performed. Thin metal and ceramic films are used extensively in the computer microprocessor industry and in the field of micro-electromechanical systems (MEMS). The demand for miniaturization and increased performance has resulted in the use of materials without a clear understanding of their mechanical properties on this scale. Micromechanical properties are difficult to obtain due to the lack of adequate testing equipment. The atomic force microscope (AFM), most commonly used as an imaging tool, lends itself to mechanical interaction with the sample surface utilizing a cantilever probe. An array of aluminum microcantilever beams were fabricated using standard IC processing techniques. The microbeams were deflected by the AFM cantilever probe and from this, the micromechanical properties of stiffness and elastic modulus were determined. Initial results indicate that this technique reliably determines the micromechanical properties of thin films.

Micromachined planar spiral inductor in standard GaAs HEMT MMIC technology

A novel free-standing planar spiral inductor with reduced parasitic capacitances is proposed by suspending individually the strips, through a maskless front-side bulk micromachining compatible with a commercial GaAs HEMT monolithic microwave integrated circuit (MMIC) technology. Suspended structures have been fabricated and characterized at frequencies up to 15 GHz, showing quality factors of up to 16 and self-resonant frequency superior to 16 GHz for a 4.8 nH inductor. Moreover, since the standard IC process as well as the unconcerned electronic circuits are not influenced by micromachining, such devices are directly useful to enhance RF circuits, like matching networks, filters, and low-noise amplifiers.

Silicon ic process compatible thin metal film post-processing module

A thin metal film post-processing module, compatible with standard IC processing, is presented. The module is based on lift-off technique and enables integration of thin metal film structures with standard microelectronic processing. A wide range of metals can be used and the technique is intended for fabrication of integrated thin metal film transducers. Typical for the module are the flexibility of metal used, the flexibility of deposition order and the low temperature at which deposition takes place. As the thermal budget of the electronics remains unaffected and the standard IC process remains intact, full compatibility is assured. Application of the module is demonstrated by fabrication of low temperature coefficient of resistance (low-TCR) NiCr resistors (minimum width 1 μm, thickness 35–75 nm, resistivity 120 μΩ cm and TCR 40 × 10 −6 K −1) and Pt/Ti resistors for on-chip local temperature measurement (Pt/Ti 80 nm/20 nm, matching Pt-100 within 2.5%).

Dry release of metal structures in oxygen plasma: process characterization and optimization

A surface micromachining fabrication scheme suitable for fabrication of free-standing metallic structures is presented. The technique is based on using conventional photoresist as a sacrificial layer, on which a metal structural layer is evaporated and patterned. The resulting structures are subsequently dry released in an isotropic oxygen plasma. For the HPR504 and HiPR6517 photoresists, a lateral underetching rate (at a power of 1000 W) of up to 1 was obtained. Structures with lateral dimensions of at least up to can be released as no etch-rate saturation for underetching beyond 20 m was observed. The process has been tested using Al as a structural layer, but any metal that can be evaporated or sputtered can be used. The presented dry-release technique is fully compatible with standard silicon IC processing and can be applied as a post-processing module. The technique eliminates any sticking problem and simplifies processing as compared to wet-etching release.

Monolithic integrated spreading-resistance silicon flow sensor

A simple integrated flow sensor, with silicon spreading-resistance (SR) as the temperature-sensing element, has been designed and fabricated by a standard IC process. The operation of this spreading-resistance silicon flow (SRSF) sensor is based on the transfer of heat from a heated chip to a flowing fluid. The temperature difference on the chip is a measure of the flow velocity. Measurements are given for velocities up to about 4 m s −1 for air at room temperature, and higher sensor output is obtained for a higher temperature difference between the chip and flow. The SRSF sensor shows good prospects in applications involving velocity and direction sensitivities, and has great potential for flows of temperature higher than the intrinsic temperature of silicon (≃ 150°C) because the SR can sense higher temperature than conventional device structures.

Surface micromachining by sacrificial aluminium etching

Sacrificial aluminium etching enables micromechanical structures integrated with circuitry to be fabricated using standard IC processes followed by simple post-processing. In this paper, the etching characteristics of CMOS aluminium in four etch solutions are reported. The solutions are (A) a commercially available aluminium etchant, (B) Krumm etch, (C) diluted hydrochloric acid, and (D) diluted hydrochloric acid with hydrogen peroxide. The etching of narrow channels is studied as a function of time and temperature. Initially, the etching process is reaction-rate controlled and then crosses over to a diffusion-controlled regime with reduced etch rate. Underetching distances larger than are readily achieved with etchants `A', `B', and `D'. The commercially available aluminium etchant has a low initial underetch rate of at but offers best control. The initial etch rate of hydrochloric acid with hydrogen peroxide is at . However, irregular etch fronts are obtained. Reliable protection of aluminium pads against etchants `A', `B', and `D' is guaranteed by Shipley's photoresist S1828 spun at 3000 rpm and hardbaked at .

Stress control of piezoelectric ZnO films on silicon substrates

Piezoelectric zinc oxide (ZnO) films are widely used for the generation and detection of acoustic waves in non-piezoelectric substrates. The application of these films on silicon offers the possibility of realizing acoustic wave devices integrated with electronic circuits, e.g. sensors. It has been demonstrated that ZnO films can be combined with standard bipolar or CMOS IC processes. However, the stress in ZnO is still an important drawback and hinders the further development of silicon integrated acoustic wave devices, particularly if the ZnO layer is deposited on thin membranes, e.g. Lamb wave devices. In this paper we discuss aspects of stress in ZnO, methods to prevent or reduce the stress and we describe an IC-compatible method for the determination of the stress in ZnO films deposited on 100 mm diameter silicon wafers.

A modified MOS IC process suitable for bulk micromachining

A method of integrating a standard IC process with bulk micromachining using KOH or EDP has been developed. Molybdenum (Mo) is used as the final metallization material because of its ability to withstand EDP and KOH etchants. Vacuum annealing is employed to enhance Mo adhesion to the nitride layer. This is especially critical for KOH etching. Experiments show that these extra steps have no deleterious effects on the MOS device characteristics.

SiO2 gate insulator defects, spatial distributions, densities, types, and sizes

Standard IC processes, as well as those involving the use of ionizing radiation, such as x-ray lithography etc., result in the generation of bulk defects, and interface states in the gate insulator, or underlying substrate, respectively, of insulated gate field effect transistors. Bulk defects are believed to be present as positively and negatively charged electron and hole traps, respectively, as well as neutral hole and “large” and “small” neutral electron traps. This paper provides a perspective of the current state of knowledge about the spatial distributions of large bulk defects, their areal densities, sizes, possible interrelationships among them, and the special cases of defects created by ion implanted silicon and oxygen, where knock-on effects have been simulated. It appears that bulk defects may all have their origin in neutral hole traps, (so-called E′ centers) and that when the insulator thickness is decreased to about 6-7 nm, defects are either no longer present, or, more likely, are incapable of trapping charge at room temperature because trapped carriers can either tunnel to one of the interfaces, or be annihilated by a reverse process. It appears possible also that the precursor of the several types of defects only forms at a “grown” silicon-silicon oxide interface. In theory, this would make it possible to grow defect free insulators by a combination of deposition and oxidation processes.

Evaluation of the fabrication of pressure sensors using bulk micromachining before IC processing

Abstract Polysilicon piezoresistive pressure sensors were fabricated in a standard IC fab, using micromachined, direct bonded silicon wafers. A standard IC process was used, and no compatibility problems were observed. Pressure sensors with excellent characteristics were obtained. Temperature coefficients of resistivity and offset (TCR and TCO) of respectively 0.084±0.004% K −1 and 0.006±0.001% K −1 were measured. The technology used gives the possibility to optimize sensitivity, overpressure protection and pressure range, even at the same time.

Thin membranes with optimized thermomechanical properties for microsystem applications

Thin polymer [poly(phenylquinoxaline)] membranes with good adhesion properties to standard metals have been produced. Chemical and mechanical integrity tests have been performed, thus showing possible applications of this material as a thermally insulating support in microthermometers and heat microsources. Thin silicon nitride membranes with a tuned stress level have also been produced. A common mechanical 'blister' test has been applied to both types of membranes. Standard IC process equipment has been used in this work.

High performance self-aligned sub-100 nm metal–oxide-semiconductor field-effect transistors using x-ray lithography

Recent studies have shown that high performance 0.1 μm complementary metal–oxide semiconductor (CMOS) can be achieved with proper channel and source/drain engineering. Specifically, retrograde channel doping and shallow source/drain junctions with counterdoping implant (halo) allow the threshold voltage to be kept low while maintaining acceptable short-channel behavior. These studies have certainly demonstrated the feasibility of CMOS technology scaled down to 0.1 μm from a device design point-of-view. However, the main challenge to the lithography technology is to fabricate 0.1 μm metal-oxide-semiconductor field-effect transistor (MOSFET) devices with high yield and high throughput, as required in manufacturing. X-ray lithography is a technology that can potentially meet this challenge. This work shows the results of integrating a low cost x-ray technology with standard IC processing to fabricate high performance 100 nm and even sub-100 nm MOSFETs.