Delay Standard Deviation Research Articles

Quantifying the Effects of Modal Conflicts on Transit Reliability

Residents of San Francisco, California, have repeatedly cited transit reliability as one of their top concerns. As San Francisco has begun investing in projects to reduce travel time variability, the trade-offs between alternatives have been difficult to quantify with existing tools. This study investigated and quantified the effects of modal conflicts on bus travel along a 3.6-mi study corridor and each conflict's contribution to unreliability. Instances of modal conflict were modeled as Bernoulli trials or other simple probabilistic events and included vehicles entering or exiting parking spaces, double-parked vehicles, and vehicles queuing for pedestrians while executing turning movements. Cumulative distributions of modal conflict resulted in estimates of average delay and variance of delay from bus to bus. Sensitivity analyses illustrated and quantified the nonlinearity and variance of delay with respect to the number and severity of events. The convolution of distributions of delay for each conflict type could also be calculated, provided the causes of delay were independent. Modal conflict delay for a side-running bus rapid transit line in the study corridor was 1.9 min longer for buses with 95th percentile delays than for those with the mean delay of 4.2 min. Overall, the semi—standard deviation of delay compared with a no-modal-conflict reference point was 4.3 min. Furthermore, eliminating the analyzed modal conflict types along the study corridor–for instance, by establishing center-running bus-only lanes–could reduce system operating costs by up to $2.5 million per year and could result in user time savings equivalent to as much as $10.5 million per year.

Capacity, Delay, and Schedule Reliability at Major Airports in Europe and the United States

Runway system capacity, air traffic delay, scheduling practices, and flight schedule reliability at major airports in Europe and the United States are compared. The comparisons are based on the study of operations at the 34 busiest airports in the United States and at the 34 busiest airports in Europe with the use of extensive data from 2007 and 2008. Major differences were found in several critical respects with important implications for aviation policy makers in both areas. U.S. airports achieve significantly higher capacities, in terms of aircraft movements, than their European counterparts with similar runway system layouts, primarily through the use of visual separation procedures when weather permits. They also achieve higher use of any available airside capacity by not placing constraints on the number of movements that can be scheduled at airports. One of the negative consequences of such policies is a high variability of delays with weather. European airports, however, limit air traffic delay by using slot controls and by determining their declared capacity (i.e., the number of slots they make available) primarily with reference to operations under instrument meteorological conditions. Particularly noteworthy is the sharp deterioration of schedule reliability over the course of a typical day at U.S. airports as measured by the expected value and the standard deviation of delay. European airports, in contrast, exhibit relatively constant schedule reliability throughout the day. A few exceptions to some of the findings are also noted on both sides of the North Atlantic.

A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates

Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This is because to maintain an acceptable noise margin level in deep sub-100 nm technologies, large pMOS keepers must be employed, which generates substantial contention between the keeper and the pull-down network, and hence results in severe loss of performance and high power consumption. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this paper, a novel variation-tolerant keeper architecture is proposed, which is capable of significantly reducing contention and improving performance and power consumption. Using circuit simulations, the overall improved characteristics of the proposed keeper are demonstrated in comparison to those of the traditional as well as several state-of-the-art keepers. The proposed keeper exhibits the lowest delay deviation under different levels of process variations. Also, it is shown that for an eight-input or gate, in presence of 15% Vth fluctuations, the proposed architecture can lead to 20%, 15%, and more than 40% reduction in power consumption, mean delay, and standard deviation of delay, respectively, when compared to the traditional keeper circuit.

Estimation of Incident Delay and Its Uncertainty on Freeway Networks

Estimating incident-induced delay on freeways is important for measuring the impacts of incidents. Information regarding delay can be used for transportation planning or the assessment of traffic improvement projects. Traditional delay estimation methods cannot account for the stochastic attributes of dynamic traffic networks. Introducing the incident duration model and the reduced capacity model into the traditional deterministic queuing model allows researchers to understand better the stochastic characteristics of dynamic networks and to develop a new stochastic incident-induced delay model. The mean delay, the variance of delay, and the expected total delay are estimated on the basis of the proposed model. The analysis shows that the deterministic queuing model can estimate the mean delay as well as the stochastic delay model, but it seriously underestimates the variance of delay and the expected total delay in dynamic networks, which are found to be dominated by incident duration. In addition, depending on the parameter values in the probability distribution of incident duration and reduced capacity, the standard deviation of delay can be higher than the mean delay.

Estimation of Incident Delay and Its Uncertainty on Freeway Networks

Estimating incident-induced delay on freeways is important for measuring the impacts of incidents. Information regarding delay can be used for transportation planning or the assessment of traffic improvement projects. Traditional delay estimation methods cannot account for the stochastic attributes of dynamic traffic networks. Introducing the incident duration model and the reduced capacity model into the traditional deterministic queuing model allows researchers to understand better the stochastic characteristics of dynamic networks and to develop a new stochastic incident-induced delay model. The mean delay, the variance of delay, and the expected total delay are estimated on the basis of the proposed model. The analysis shows that the deterministic queuing model can estimate the mean delay as well as the stochastic delay model, but it seriously underestimates the variance of delay and the expected total delay in dynamic networks, which are found to be dominated by incident duration. In addition, depending on the parameter values in the probability distribution of incident duration and reduced capacity, the standard deviation of delay can be higher than the mean delay.

Reduced delay sensitivity to process induced variability in current sensing interconnects

The effect of process induced variability in long global on-chip interconnects caused by critical dimension control and intrinsic fluctuation of transistor threshold voltage is analysed for current and voltage mode signalling. Projections in scaled CMOS technologies show that current sensing interconnects exhibit smaller mean delay and sensitivity to parameter fluctuations. The standard deviation of delay exhibits an increasing dependency on process variations at the low and high extremes of receiver to driver circuit resistance ratios. An experimental on-chip bus demonstrates the reduced delay variability in current sensing schemes.

Virtual-FIFO Back-Off Algorithm for Collision Resolution in Wireless Networks

This investigation proposes a virtual-FIFO (VFIFO) back-off algorithm for wireless networks. The proposed scheme takes advantage of the central unit (CU) in a wireless network to broadcast a common back-off window size to all the users, significantly alleviating the unfairness of bandwidth utilization in conventional binary exponential back-off (BEB) algorithms. The proposed scheme exploits the CU's capability for collision detection to estimate the number of simultaneously competing users. Additionally, packets generated in a given cycle are split into groups according to their times of arrivals and are guaranteed to be serviced one after another within the next cycle. Although the proposed algorithm is not strictly first come fist served, the FIFO principle is virtually accomplished. Simulation results demonstrate that the standard deviation of delay can be improved by more than two orders and the throughput can be maintained at 0.42 when the number of users approaches infinity. The capture effect even further improves system performance.

Enhanced Simulation Inference Using Bootstraps of Historical Inputs

Simulation input analysis can present a dilemma: either use one historical trace that is realistic but captures only a small portion of the possible input variability, or use many unrealistic inputs generated by simplified parametric models of the trace. We demonstrate that a nonparametric time series bootstrap can ease the dilemma by converting a single trace into many realistic input scenarios. Bootstrapping inputs reduces by about one-third the inaccuracy in estimated standard errors for mean delay, standard deviation of delay, and probability of long delay in a G/M/1 queue. Such improvements can be achieved without an increase in the number of simulation runs by reducing the number of non-trace input replications to offset the increased number of inputs created by bootstrapping the trace. Bootstrapping can also be applied in problems lacking other means of estimating uncertainty in system performance. We show an example in system reliability where reasonable estimates are available over a wide range of bootstrap block sizes. We note that bootstrap estimates are always conditional on the traces from which they derive and thereby tend to underestimate the true level of uncertainty. Nevertheless, bootstrapping inputs offers a new way to enhance statistical inference in simulation experiments.

Prediction and Measurement of Travel Time Along Pedestrian Routes

A methodology to predict the walking and queueing times on pedestrian routes is developed. Walking time predictions are based on either average pedestrian space or flow rate. Queueing time estimates at signalized intersections are based on an assumption of random arrivals. The methodology is tested by comparing travel time predictions with the results of travel time runs on several routes near the city center of Brisbane, Australia. Data from 49 signalized intersections within the routes indicate that upstream coordinated signals can significantly affect downstream signal delay. It was also found that, in a coordinated signal system, the standard deviation of delay at a signal can be much different from what would be expected if arrivals were random. The effect of signal coordination on average delay was also apparent at the arterial level.

Submesh Allocation in Mesh Multicomputers Using Busy-List: A Best-Fit Approach with Complete Recognition Capability

A new approach is proposed for dynamic submesh allocation in mesh-connected multicomputer system, which supports a multiuser environment. The proposed strategy effectively prunes the search space by searching for free submeshes on the corners of allocated (busy) submeshes along with the four corners of the mesh system. A submesh is selected with the potential of causing the least amount of fragmentation in the system. The proposed strategy possesses complete submesh recognition capability; it is a best-fit strategy, as well. Existing strategies do not provide this combination of capabilities. The deallocation time and memory overhead are shown to be constant in that they do not grow with the size of the mesh. To demonstrate effectiveness, the performance of the proposed strategy is compared against all existing schemes. Simulation results indicate that the proposed strategy outperforms existing ones in terms of parameters such as average delay in honoring a request, standard deviation of delay, average allocation time, average deallocation time, and amount of memory required. The proposed scheme achieves a 20 to 30% improvement in the average waiting delay over the best performing existing algorithm to date. Our scheme is shown to be applicable to torus-connected multicomputers as well, with only minor modifications. The scheme can also be used for submesh allocation with failures.