Standard Complementary Metal Oxide Semiconductor Process Research Articles

Superior Temperature-Sensing Performance in Cladding-Modulated Si Waveguide Gratings

This paper presents a silicon photonic temperature sensor based on a complementary metal-oxide-semiconductor (CMOS) compatible cladding-modulated (CladMod) grating design on the silicon-on-insulator platform. The resulting device achieves narrow-band reflection (Δλ = 0.63 nm), a high extinction ratio (21 dB), high temperature sensitivity (83.4 pm/°C), and a wide temperature-sensing range. More importantly, this grating design allows stable reflection bandwidth $\rm{(\Delta \lambda / \Delta W}_{\rm{g}}\,\rm{ = 0.013)}$ , Bragg wavelength $\rm{(\lambda }_{\rm{B }}\rm{/ \Delta W}_{\rm{g}}\,\rm{ = 0.002)}$ , and temperature sensitivity $\rm{(\delta \lambda / \delta T/ \Delta W}_{\rm{g}}\,\rm{ = - 1.3\times 10}^{- 5}\rm{ K}^{- 1}\rm{)}$ against variations in grating width. This level of temperature-sensing performance is difficult to achieve using a strip/slab-type grating or microring resonator. The CladMod gratings were further implemented on a polysilicon gate in a standard bulk CMOS process, thereby enabling integration with other microelectronic devices to serve as an on-chip distributed temperature-sensing element This approach shows considerable promise for applications such as future photonic-electronic integrated circuits requiring in situ temperature monitoring for wavelength stabilization, or high-temperature microelectronics where silicon bandgap temperature sensors are unable to operate properly

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The focal plane array has been fully integrated in a m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band G-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of nW at 270 GHz and nW at 600 GHz.

A CMOS image sensor with variable frame rate for low-power operation

In this paper, a complementary metal oxide semiconductor (CMOS) image sensor for low-power operation with a variable frame rate is presented. The operating current of the CIS can be reduced by varying the frame rate of the CMOS image sensor (CIS), thus decreasing power consumption effectively. The proposed image sensor has two modes: normal mode and lowpower mode. In the low-power mode, the operating current of the pixel array can be controlled according to the frame rate of the CIS. At lower frame rates, the operating current of the pixel array is smaller than in the normal mode. The power consumption of the proposed CIS is determined by the on and off ratios of the bias current. The proposed image sensor was fabricated and measured with a 2-poly 4-metal 0.35 μm standard CMOS process.

Compact SOI Polarization Rotator Using Asymmetric Periodic Loaded Waveguides

We demonstrate the design and experimental results of a silicon-on insulator (SOI) polarization rotator design based on asymmetric periodically loaded waveguides. The rotator design features a compact device footprint of 15.78 $\mu\mbox{m}$ , with a measured polarization rotation extinction ratio of 11.8 dB at 1525 nm while maintaining at least 6 dB ER over the entire C-band. The fabrication of this rotator is fully compatible with the standard complementary metal-oxide semiconductor (CMOS) process with a SiO2 top cladding. So far, this is the most compact polarization rotator demonstration utilizing the asymmetric periodically loaded SOI waveguides. However, the device is sensitive to fabrication errors; thus, the performance is limited by the current fabrication technology.

Multifunctional Platform with CMOS-Compatible Tungsten Microhotplate for Pirani, Temperature, and Gas Sensor

A multifunctional platform based on the microhotplate was developed for applications including a Pirani vacuum gauge, temperature, and gas sensor. It consisted of a tungsten microhotplate and an on-chip operational amplifier. The platform was fabricated in a standard complementary metal oxide semiconductor (CMOS) process. A tungsten plug in standard CMOS process was specially designed as the serpentine resistor for the microhotplate, acting as both heater and thermister. With the sacrificial layer technology, the microhotplate was suspended over the silicon substrate with a 340 nm gap. The on-chip operational amplifier provided a bias current for the microhotplate. This platform has been used to develop different kinds of sensors. The first one was a Pirani vacuum gauge ranging from 1-1 to 105 Pa. The second one was a temperature sensor ranging from -20 to 70 °C. The third one was a thermal-conductivity gas sensor, which could distinguish gases with different thermal conductivities in constant gas pressure and environment temperature. In the fourth application, with extra fabrication processes including the deposition of gas-sensitive film, the platform was used as a metal-oxide gas sensor for the detection of gas concentration.

Development of Silicon Probe With Acute Study on <italic>In Vivo</italic> Neural Recording and Implantation Behavior Monitored by Integrated Si-Nanowire Strain Sensors

The silicon probe with highly P-doped Si electrodes was realized on 8-in Silicon on insulator wafer through standard Complementary metal-oxide semiconductor process. By leveraging the same thin Si device layer ( $\sim 100$ nm), the built-in piezoresistive Si-nanowires (SiNWs) configured in full-bridge structure were also equipped along the probe shank for strain sensing. After additional coatings of nanocomposite (Carbon nanotubes + Au nanoparticles) on silicon electrodes, the functionality of neural recording was validated with a low noise level ( $ ) during in vivo neural recording on rat brain (CA1 region). The additional capability of monitoring probe mechanical behavior was first verified through the probe buckling experiments and further examined with implantations on rat brain (S1 region). Besides the large buckling mechanics, the physiological brain micromotion (e.g., caused by respiration) was successfully picked up by integrated SiNWs strain sensors, which would provide the research platform to practically understand the correlation between the electrical neural signal and the brain micromotion. [2014-0370]

Spatial optical crosstalk in CMOS image sensors integrated with plasmonic color filters.

Imaging resolution of complementary metal oxide semiconductor (CMOS) image sensor (CIS) keeps increasing to approximately 7k × 4k. As a result, the pixel size shrinks down to sub-2μm, which greatly increases the spatial optical crosstalk. Recently, plasmonic color filter was proposed as an alternative to conventional colorant pigmented ones. However, there is little work on its size effect and the spatial optical crosstalk in a model of CIS. By numerical simulation, we investigate the size effect of nanocross array plasmonic color filters and analyze the spatial optical crosstalk of each pixel in a Bayer array of a CIS with a pixel size of 1μm. It is found that the small pixel size deteriorates the filtering performance of nanocross color filters and induces substantial spatial color crosstalk. By integrating the plasmonic filters in the low Metal layer in standard CMOS process, the crosstalk reduces significantly, which is compatible to pigmented filters in a state-of-the-art backside illumination CIS.

A Two-Phase Fully-Integrated DC–DC Converter With Self-Adaptive DCM Control and GIPD Passive Components

This paper presents a two-phase fully-integrated dc–dc converter for system-in-package systems with passive components fabricated using a glass-substrate-integrated passive device (GIPD) process. The proposed self-adaptive discontinuous conduction mode (DCM) controller and low-swing/full-swing buffer were incorporated to reduce the switching loss and maintain high efficiency at high switching frequency. A secondary phase and phase controller were added to increase the output power and reduce the output ripple. The proposed GIPD solution packages a standard complementary metal–oxide–semiconductor process and GIPD process in 3-D format to reduce the footprint of the system. The proposed self-adaptive DCM controller and low-swing/full-swing buffer improve efficiency of 15% in measurement compared to our previous work on the GIPD process in simulation. The peak efficiency of the proposed converter was 79.09% at a 400-mA load current, 5% higher than the peak efficiency presented in previous study. The maximal output power could reach 720 mW and the maximal switching frequency ( $f_{{\rm CCM}}$ ) was designed to be 70 MHz (measured at 50 MHz) with only two 6-nH inductors and one 15-nF capacitor.

A novel CMOS-MEMS integrated pressure sensing structure based on current mirror sensing technique

Purpose– The present paper aims to propose a basic current mirror-sensing circuit as an alternative to the traditional Wheatstone bridge circuit for the design and development of high-sensitivity complementary metal oxide semiconductor (CMOS)–microelectromechanical systems (MEMS)-integrated pressure sensors.Design/methodology/approach– This paper investigates a novel current mirror-sensing-based CMOS–MEMS-integrated pressure-sensing structure based on the piezoresistive effect in metal oxide field effect transistor (MOSFET). A resistive loaded n-channel MOSFET-based current mirror pressure-sensing circuitry has been designed using 5-μm CMOS technology. The pressure-sensing structure consists of three identical 10-μm-long and 50-μm-wide n-channel MOSFETs connected in current mirror configuration, with its input transistor as a reference MOSFET and output transistors are the pressure-sensing MOSFETs embedded at the centre and near the fixed edge of a silicon diaphragm measuring 100 × 100 × 2.5 μm. This arrangement of MOSFETs enables the sensor to sense tensile and compressive stresses, developed in the diaphragm under externally applied pressure, with respect to the input reference transistor of the mirror circuit. An analytical model describing the complete behaviour of the integrated pressure sensor has been described. The simulation results of the pressure sensor show high pressure sensitivity and a good agreement with the theoretical model has been observed. A five mask level process flow for the fabrication of the current mirror-sensing-based pressure sensor has also been described. An n-channel MOSFET with aluminium gate was fabricated to verify the fabrication process and obtain its electrical characteristics using process and device simulation software. In addition, an aluminium gate metal-oxide semiconductor (MOS) capacitor was fabricated on a two-inch p-type silicon wafer and its CV characteristic curve was also measured experimentally. Finally, the paper presents a comparative study between the current mirror pressure-sensing circuit with the traditional Wheatstone bridge.Findings– The simulated sensitivities of the pressure-sensing MOSFETs of the current mirror-integrated pressure sensor have been found to be approximately 375 and 410 mV/MPa with respect to the reference transistor, and approximately 785 mV/MPa with respect to each other. The highest pressure sensitivities of a quarter, half and full Wheatstone bridge circuits were found to be approximately 183, 366 and 738 mV/MPa, respectively. These results clearly show that the current mirror pressure-sensing circuit is comparable and better than the traditional Wheatstone bridge circuits.Originality/value– The concept of using a basic current mirror circuit for sensing tensile and compressive stresses developed in micro-mechanical structures is new, fully compatible to standard CMOS processes and has a promising application in the development of miniaturized integrated micro-sensors and sensor arrays for automobile, medical and industrial applications.

A differential coupled frequency doubling voltage-controlled crystal oscillator in a 0.35 μm CMOS process

This paper presents a high-performance differential coupled frequency doubling voltage-controlled crystal oscillator (VCXO). Frequency doubling and low phase noise are realized through a novel gm-boosted differential Colpitts oscillator. Distributed varactor arrays are used to obtain wide frequency tuning range and high tuning linearity simultaneously. The proposed VCXO is fabricated in a 0.35 μm 2P3M standard complementary metal-oxide semiconductor process at a supply voltage of 3.3 V, and the power dissipation is 7 mW. Measurement results show that the designed VCXO achieves ±135 ppm output frequency variation range with 5 % linearity and ?133 dBc/Hz phase noise at 1 kHz frequency offset by using a 40 MHz fundamental AT-cut crystal resonator.

Compact silicon-on-insulator-based 2 \times 2 Mach–Zehnder interferometer electro-optic switch with low crosstalk

We report a compact 2×2 Mach–Zehnder interferometer (MZI) electro-optic switch fabricated on a silicon-on-insulator using standard complementary metal-oxide semiconductor (CMOS) processes. With a short modulation arm length of 200 μm, the crosstalk is reduced to −22 dB by the new modulation scheme of push–pull modulation with a pre-biased π/2 phase shift. The new modulation scheme can also work with a fast switching time of about 5.4 ns.

Design and optimization of backside illuminated image sensor for epiretinal implants

Backside illuminated pixel structure is proposed and evaluated as the building block for the image sensor being used as epiretinal prosthesis implant. The image sensor pixel is designed with the parameters of 90nm technology node of standard CMOS (Complementary Metal Oxide Semiconductor) process. The image sensor is consisted of a p-sub/n-well structure as the photosensitive area with the pixel pitch of 20μm. The maximum fill factor is observed due to separation of photosensitive area with the readout transistor surface in backside illumination technology. 90% quantum efficiency at 600nm wavelength and the dark current of 74.6nA/cm2 at room temperature is achieved for the optimized pixel. The application of deep backside Deep Trench Isolation (DTI), with high depth n-well doping profiles, results in a significant reduction of crosstalk (5.6% total crosstalk).

Low‐jitter, high‐linearity current‐controlled complementary metal oxide semiconductor relaxation oscillator with optimised floating capacitors

A new complementary metal oxide semiconductor (CMOS) relaxation oscillator featuring with high linearity and low-jitter is presented in this study. The high linearity between the frequency and control current is achieved by adopting the floating capacitor and the independent charged and discharged loops. The low-jitter performance is gained because of that the voltage across the floating capacitor is larger than the conventional oscillator. The proposed circuit is compatible with standard CMOS process and one test-chip with typical frequency of 6.66 MHz was implemented in the 0.5 μm (bipolar–CMOS–double-diffused metaloxide semiconductor (DMOS)) (BCD) process. The measured results show that <0.86% non-linearity in the current–frequency transfer function from 1 to 6.66 MHz without trimming. The cycle-to-cycle jitter was <112 ppm.

Improved performance and low cost OLED microdisplay with titanium nitride anode

This work experimented on the TEOLED (Top-emitting Organic Light-Emitting Diode) using the TiN (titanium nitride) as the anode for the microdisplays based on the CMOS (Complementary Metal–Oxide–Semiconductor) integrated circuit substrate. TiN is a hard, dense, and refractory material with steady physical and chemical characteristics. It is proved in this work to be a good candidate for the anode of the TEOLED due to its good electrical and optical characteristics. A SXGA resolution OLED microdisplay is designed and developed with TiN anodes. The luminance reaches beyond 2700cd/m2 when the operating voltage is below 5V. The power efficiency reaches 13lm/W at the luminance of 1000cd/m2. As a conclusion, TiN can be used to solve the incompatibility problem between the CMOS process and the OLED process. By fabricating the top metal coated with TiN as the TEOLED anodes in the standard CMOS process, it is not necessary to build a new separate post-process line for the anodes in the mass manufacture. Hence, the process step for the CMOS-based OLED microdisplay will be simplified, huge cost will be saved and the production yield will also be improved.

Electric field manipulation of nonvolatile magnetization in Au/NiO/Pt heterostructure with resistive switching effect

The electrical field manipulation of magnetization is investigated in an Au/NiO/Pt heterostructure, which is fully compatible with the standard complementary metal-oxide semiconductor process. Reversible and stable unipolar resistive switching effects as well as a significant nonvolatile change of the magnetization are observed in this device during the set and reset processes at room temperature. Further analysis indicates that the formation and rupture of metallic Ni conducting filaments caused by the electric field would be responsible for the changes of resistivity and magnetization. The coexistence of the electric field control of magnetization change and resistive switching makes Au/NiO/Pt heterostructure a promising candidate for the multifunctional memory devices.

Spin nano-oscillator-based wireless communication.

Spin–torque nano–oscillators (STNOs) have outstanding advantages of a high degree of compactness, high–frequency tunability, and good compatibility with the standard complementary metal–oxide–semiconductor process, which offer prospects for future wireless communication. There have as yet been no reports on wireless communication using STNOs, since the STNOs also have notable disadvantages such as lower output power and poorer spectral purity in comparison with those of LC voltage–controlled oscillators. Here we show that wireless communication is achieved by a proper choice of modulation scheme despite these drawbacks of STNOs. By adopting direct binary amplitude shift keying modulation and non–coherent demodulation, we demonstrate STNO–based wireless communication with 200–kbps data rate at a distance of 1 m between transmitter and receiver. It is shown, from the analysis of STNO noise, that the maximum data rate can be extended up to 1.48 Gbps with 1–ns turn–on time. For the fabricated STNO, the maximum data rate is 5 Mbps which is limited by the rise time measured in the total system. The result will provide a viable route to real microwave application of STNOs.

Design and Development of X-band Planar Balun on Silicon

This article presents the design and realization of an X-band (8.2 GHz) planar balun using microstrip technology. Further, various materials compatible to standard Complementary metal-oxide semiconductor (CMOS) process are analyzed, and the optimum process which is combination of plasma-enhanced chemical vapor deposition (PECVD) oxide and high-resistivity wafer is selected for better RF performance. The performance of the balun is optimized by electromagnetic analysis and realized on silicon substrate utilizing CMOS process. The measured results show close agreement with simulation having amplitude imbalance of ±0.35 dB (max.), return loss better than 14 dB (min.), and a maximum phase error of ±0.75° at the designed frequency.

Extension of the Dynamic Range in the CMOS Active Pixel Sensor Using a Stacked Photodiode and Feedback Structure

This paper presents an extension of the dynamic range in a complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) using a stacked photodiode and feedback structure. The proposed APS is composed of two additional MOSFETs and stacked P+/N-well/P-sub photodiodes as compared with a conventional APS. Using the proposed technique, the sensor can improve the spectral response and dynamic range. The spectral response is improved using an additional stacked P+/N-well photodiode, and the dynamic range is increased using the feedback structure. Although the size of the pixel is slightly larger than that of a conventional three-transistor APS, control of the dynamic range is much easier than that of the conventional methods using the feedback structure. The simulation and measurement results for the proposed APS demonstrate a wide dynamic range feature. The maximum dynamic range of the proposed sensor is greater than 103 dB. The designed circuit is fabricated by the <TEX>$0.35-{\mu}m$</TEX> 2-poly 4-metal standard CMOS process, and its characteristics are evaluated.

Efficient premature edge breakdown prevention in SiAPD fabrication using the standard CMOS process

The effects of premature edge breakdown (PEB) and available PEB prevention (PEBP) techniques in silicon avalanche photodiode fabrication using the standard complementary metal–oxide–semiconductor (CMOS) process are scrutinized in this paper. Impact of device simulation and its induced impacts on fabrication are addressed based on our design, simulation and fabrication experiences. Three most common PEBP techniques are implemented followed by a systematic study aimed at miniaturization, while optimizing the overall performance. The p-well-, p-sub- and n-well-based PEBP techniques are evaluated and compared based on simulation and fabrication results using the standard CMOS process. The results demonstrate that the n-well guard ring offers the most efficient PEBP technique. This technique offers a high-gain (∼800), low-noise dark current rate (DCR = 40 Hz), high detection efficiency (70%) avalanche photodiode with a higher functionality probability.

Atomic layer-deposited Al–HfO2/SiO2 bi-layers towards 3D charge trapping non-volatile memory

A metal/oxide/high-κ dielectric/oxide/silicon (MOHOS) planar charge trapping memory capacitor including SiO2 as tunnel oxide, Al–HfO2 as charge trapping layer, SiO2 as blocking oxide and TaN metal gate was fabricated and characterized as test vehicle in the view of integration into 3D cells. The thin charge trapping layer and blocking oxide were grown by atomic layer deposition, the technique of choice for the implementation of these stacks into 3D structures. The oxide stack shows a good thermal stability for annealing temperature of 900°C in N2, as required for standard complementary metal–oxide–semiconductor processes. MOHOS capacitors can be efficiently programmed and erased under the applied voltages of ±20V to ±12V. When compared to a benchmark structure including thin Si3N4 as charge trapping layer, the MOHOS cell shows comparable program characteristics, with the further advantage of the equivalent oxide thickness scalability due to the high dielectric constant (κ) value of 32, and an excellent retention even for strong testing conditions. Our results proved that high-κ based oxide structures grown by atomic layer deposition can be of interest for the integration into three dimensionally stacked charge trapping devices.