Abstract
The effects of premature edge breakdown (PEB) and available PEB prevention (PEBP) techniques in silicon avalanche photodiode fabrication using the standard complementary metal–oxide–semiconductor (CMOS) process are scrutinized in this paper. Impact of device simulation and its induced impacts on fabrication are addressed based on our design, simulation and fabrication experiences. Three most common PEBP techniques are implemented followed by a systematic study aimed at miniaturization, while optimizing the overall performance. The p-well-, p-sub- and n-well-based PEBP techniques are evaluated and compared based on simulation and fabrication results using the standard CMOS process. The results demonstrate that the n-well guard ring offers the most efficient PEBP technique. This technique offers a high-gain (∼800), low-noise dark current rate (DCR = 40 Hz), high detection efficiency (70%) avalanche photodiode with a higher functionality probability.
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