Standard Complementary Metal Oxide Semiconductor Process Research Articles

Improving the Performance of Antenna-on-Chip by Effectively Illuminating the Artificial Magnetic Conductors Through Coupling Enhancement Structures

An antenna-on-chip (AoC) suffers from low radiation efficiency and gain because of the highly conductive silicon substrate used in standard complementary metal–oxide–semiconductor (CMOS) processes. Placing an artificial magnetic conductor (AMC) surface underneath the AoC not only isolates the antenna from the lossy substrate but also boosts its performance through in-phase reflection. Ideally, the AMC, which has a periodic structure, should be infinite in size, but practical chip sizes limit its dimensions. The gain of an AMC-backed AoC shows a positive correlation with the AMC lateral area. However, in the ultrathin stack-up of standard CMOS processes, the AMC cannot be irradiated uniformly by the antenna because of the physical illumination issue, so the AoC gain does not increase with the AMC area after the initial increase. To improve the illumination of the AMC by an AoC, this work introduces coupling enhancement structures (CES) that employ the available metal layers of the stack-up. The proposed AMC-backed AoC with CES demonstrates a gain of 9.8 dBi and radiation efficiency of 71% at 94 GHz, which are improvements of 4.3 dB in gain and 23% in radiation efficiency, respectively, compared to an AoC backed by a conventional AMC.

A Miniaturized CMOS-MEMS Amperometric Gas Sensor for Rapid Ethanol Detection

This study presents the design and implementation of a chip-scale amperometric ethanol sensor using the standard commercially available complementary metal oxide semiconductor (CMOS) process together with the post-CMOS micromachining processes. The presented amperometric sensor consists of a suspended plate with a microhole structure as the working electrode, a fully anchored plate with a microhole structure as the counter electrode, and a microcavity as the electrolyte reservoir. The metal and dielectric layers inherent in the standard CMOS process are exploited to realize these structures. The electrode with a microhole structure could enhance its surface area to improve the sensitivity of the sensor. The suspended working electrode covered a thinner Nafion <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text {R}}$ </tex-math></inline-formula> layer could facilitate gas diffusion to shorten the response time of the sensor. To characterize the ethanol sensing, a Ni film is deposited on the working electrode. Measurements indicate the presented sensor has a sensing range of ppm (20–1000 ppm) at room temperature. Moreover, its sensitivity and response time are, respectively, 0.01 nA/ppm and 6 s. The presented design shows the CMOS-MEMS is a promising approach to realize the amperometric ethanol sensor.

A CNN-Based E-Nose Using Time Series Features for Food Freshness Classification

In this article, a convolutional neural network (CNN)-based electronic nose system is proposed, which utilizes time series features to classify the freshness of food. The electronic nose is composed of three elements: a highly sensitive miniaturized micro-electromechanical systems (MEMS) metal–oxide (MOX)–semiconductor gas sensor array, a complementary metal–oxide–semiconductor (CMOS) integrated circuit, and a CNN-based classification unit. The gas sensors exhibit exceptional sensitivity, low power consumption, and a small size. The interface circuit for sensor readout is fabricated using a standard 180-nm CMOS process, with an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times1.5$ </tex-math></inline-formula> mm. The interface chip mainly consists of an analog-to-digital converter (ADC), an electrically erasable programmable read-only memory (EEPROM), an oscillator (OSC), power management, a heater driver, and a digital control circuit. Fixed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}{(}{t}{)}$ </tex-math></inline-formula> exposures are taken at specific intervals under gas input and output conditions. Time series features are extracted from a diverse set of sensor signals, which allows the subtle differences in various food odors at different freshness levels to be identified. The incorporation of time series feature extraction extends the data features, resulting in enhanced classification accuracy with a limited number of sensors. An abstract odor map input to the CNN is formed by combining the steady-state and transient information of the gas sensor response. The final freshness classification accuracy of 20 types of foods is 97.3%. The accuracy is improved by 6.5% after the implementation of time series feature extraction, demonstrating the significance of instantaneous fluctuation information for classification accuracy.

High-performance one-dimensional MOSFET array photodetectors in the 0.8-µm standard CMOS process.

This paper reports a series of novel photodetectors based on one-dimensional array of metal-oxide-semiconductor field-effect transistors (MOSFETs), which were fabricated using the standard 0.8-µm complementary metal oxide semiconductor (CMOS) process. Normally, the metal fingers of MOSFET must be manufactured above active region in standard CMOS process, causing MOSFET insensitive to light. The proposed photodetectors use the metal fingers of MOSFETs in a one-dimensional array to form periodical slit structures, which make the transmittance of incident light higher, due to the surface plasmons (SPs) resonance effect. The number of parallel MOSFETs in one-dimensional array is 3, 5, 7, 9 and 11. The experimental results show that all responsivities (Rv) are greater than 103 A/W within visible and near-infrared spectra under room temperature and a maximum value of 1.40 × 105 A/W is achieved, which is at least one order of magnitude larger than those of published photodetectors. Furthermore, a minimum noise equivalent power (NEP) of 5.86 fW/Hz0.5 at 30 Hz and a maximum detectivity (D*) of 2.21 × 1013 Jones are obtained. The photodetectors still have good signal-to-noise ratio when the bandwidth is 1 GHz. At the same time, the optical scanning imaging was completed by utilizing the photodetectors. This combination of high Rv, excellent NEP, high speed and broad spectrum range photodetectors will be widely used in imaging systems.

Design, fabrication, characterization and reliability study of CMOS-MEMS Lorentz-force magnetometers

This article presents several design techniques to fabricate micro-electro-mechanical systems (MEMS) using standard complementary metal-oxide semiconductor (CMOS) processes. They were applied to fabricate high yield CMOS-MEMS shielded Lorentz-force magnetometers (LFM). The multilayered metals and oxides of the back-end-of-line (BEOL), normally used for electronic routing, comprise the structural part of the MEMS. The most important fabrication challenges, modeling approaches and design solutions are discussed. Equations that predict the Q factor, sensitivity, Brownian noise and resonant frequency as a function of temperature, gas pressure and design parameters are presented and validated in characterization tests. A number of the fabricated magnetometers were packaged into Quad Flat No-leads (QFN) packages. We show this process can achieve yields above 95 % when the proper design techniques are adopted. Despite CMOS not being a process for MEMS manufacturing, estimated performance (sensitivity and noise level) is similar or superior to current commercial magnetometers and others built with MEMS processes. Additionally, typical offsets present in Lorentz-force magnetometers were prevented with a shielding electrode, whose efficiency is quantified. Finally, several reliability test results are presented, which demonstrate the robustness against high temperatures, magnetic fields and acceleration shocks.

Integrated acoustic resonators in commercial fin field-effect transistor technology

In radio communication, the growth of beamforming and multiple-input–multiple-output technologies, which increase transceiver complexity, have led to a drive to reduce the size, weight and power of radio components by integrating them into a single system on chip. One approach is to integrate the frequency references of acoustic microelectromechanical systems (MEMS) with complementary metal–oxide–semiconductor processes, typically through a MEMS-first or MEMS-last approach that requires process customization. Here we report unreleased acoustic resonators that are fabricated in 14 nm fin field-effect transistor technology and operate in the X-band frequency range (8–12 GHz). The devices use phononic waveguides for acoustic confinement and exploit metal–oxide–semiconductor capacitors and transistors to electromechanically drive and sense acoustic vibrations. Fifteen device variations are analysed across 30 bias points, quantifying the importance of phononic confinement on resonator performance and demonstrating the velocity-saturated piezoresistive effect in active resonant transistors. Our results illustrate the feasibility of integrating acoustic devices directly into standard complementary metal–oxide–semiconductor processes.

A Highly Reliable and Energy-Efficient Schmitt Trigger PUF Featuring Ultra-Wide Supply Voltage Range

In this brief, we present a Schmitt trigger physical unclonable function (ST-PUF) featuring high reliability under ultra-low supply voltage. By replacing the standard complementary-metal-oxide-semiconductor (CMOS) inverter of traditional static random access memory (SRAM) PUFs to ST inverter, the relatively large transition width can be significantly reduced by 1.91~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$121.8\times $ </tex-math></inline-formula> under different supply voltage and temperature (VT) conditions. This leads to dramatically enhanced reliability against the environmental noise and VT variations. The proposed implementation is validated using a 65-nm 1.2 V standard CMOS process, and the reference supply voltage is optimized to be 0.4 V, in order to strike an excellent balance between the power/energy consumption and the reliability. According to our extensive post-layout simulation results, the worst-case bit error rate (BER) is reported to be 2.14% with the supply voltage varying from 0.3 V to 0.5 V and the temperature varying from −40°C to 120°C. The core energy consumption is simulated to be 2.31 fJ/bit at a throughput of 160 Mb/s. Moreover, the generated raw PUF bits have passed both the National Institute of Standards and Technology (NIST) and auto-correlation function (ACF) randomness tests.

Fully integrated parity\u2013time-symmetric electronics

Harnessing parity–time symmetry with balanced gain and loss profiles has created a variety of opportunities in electronics from wireless energy transfer to telemetry sensing and topological defect engineering. However, existing implementations often employ ad hoc approaches at low operating frequencies and are unable to accommodate large-scale integration. Here we report a fully integrated realization of parity–time symmetry in a standard complementary metal–oxide–semiconductor process technology. Our work demonstrates salient parity–time symmetry features such as phase transition as well as the ability to manipulate broadband microwave generation and propagation beyond the limitations encountered by existing schemes. The system shows 2.1 times the bandwidth and 30% noise reduction compared to conventional microwave generation in the oscillatory mode, and displays large non-reciprocal microwave transport from 2.75 to 3.10 GHz in the non-oscillatory mode due to enhanced nonlinearities. This approach could enrich integrated circuit design methodology beyond well-established performance limits and enable the use of scalable integrated circuit technology to study topological effects in high-dimensional non-Hermitian systems.

Silicon-integrated high-speed mode and polarization switch-and-selector

On-chip optical communications are growingly aiming at multimode operation together with mode-division multiplexing to further increase the transmission capacity. Optical switches, which are capable of optical signals switching at the nodes, play a key role in optical networks. We demonstrate a 2 × 2 electro-optic Mach–Zehnder interferometer-based mode- and polarization-selective switch fabricated by standard complementary metal–oxide–semiconductor process. An electro optic tuner based on a PN-doped junction in one of the Mach–Zehnder interferometer arms enables dynamic switching in 11 ns. For all the channels, the overall insertion losses and inter-modal crosstalk values are below 9.03 and –15.86 dB at 1550 nm, respectively.

Design of a CMOS image sensor pixel with embedded polysilicon nano-grating for near-infrared imaging enhancement.

Complementary metal-oxide semiconductor (CMOS) image sensor sensitivity in the near-infrared spectrum is limited by the absorption length in silicon. To deal with that limitation, we evaluate the implementation of a polysilicon nano-grating inside a pixel, at the transistor gate level of a 90 nm standard CMOS process, through opto-electrical simulations. The studied pixel structure involves a polysilicon nano-grating, designed with the fabrication layer of the transistor gate, which does not require any modifications in the process flow. The diffraction effect of the nano-grating increases the length of the light path in the photosensitive area and thus increases the photoelectric conversion efficiency. The nano-grating is integrated in combination with deep trench isolations to reduce cross talk between pixels. Coupled optical and electrical simulations report 33% external quantum efficiency improvement and 7% cross talk reduction at 850 nm.

A comprehensive review of FET‐based pH sensors: materials, fabrication technologies, and modeling

AbstractThe demand for miniaturized point‐of‐care chemical/biochemical sensors has driven the development of field‐effect transistors (FETs) based pH sensors over the last 50 years. This paper aims to review the fabrication technologies, device structures, sensing film materials, and modeling techniques utilized for FET‐based pH sensors. We present the governing principles of potentiometric sensors, with major focus on the working principles of ion‐sensitive FETs (ISFETs). We extensively review different sensing film materials deposited by various techniques, which is critical to the sensing performance of ISFETs. The popular fabrication technologies have been presented, with special emphasis on state‐of‐the‐art silicon‐on‐insulator based technology, which can achieve high sensitivity by utilizing the dual‐gate effect. Furthermore, recent advancements in nano‐ISFETs has been elucidated. We also discuss the adoption of unmodified complementary metal‐oxide semiconductor (CMOS) ISFETs using standard CMOS processes, which has enabled the fabrication of integrated ISFET arrays, which are especially suited for ion‐imaging applications. Moreover, recent developments in extended‐gate FETs has been discussed, which have gained lot of attention due to their design flexibility and ease of fabrication, which is desirable for wearable sensing applications. In addition, recently there have been efforts to utilize nonsilicon channel materials for pH‐sensing application to obtain superior performance and various channel materials have been reviewed. Finally, we have extensively reviewed the ISFET device modeling and simulation techniques using various computer‐aided design tools, which aid in sensor design and characterization.

Folded 15-channel arrayed waveguide gratings on silicon nitride platform with loop reflector

Silicon nitride (Si3N4) arrayed waveguide gratings (AWGs) have been widely used for dense wavelength division multiplexing systems because of their low loss and crosstalk. However, they have larger footprints because of their lower relative index compared with silicon-on-insulator (SOI) devices. In this study, a folded 1×15 Si3N4 AWG was fabricated on an SOI wafer with a silicon photonics loop reflector. The combination of the Si3N4 AWG and the Si loop reflector greatly reduced the device footprint and increased the fabrication tolerances. A layer coupler was used to connect the arrayed waveguides of the AWG to the Si loop reflector. The folded AWG consisted of a half Si3N4 AWG structure, an layer coupler array, and a Si loop reflector array. The measured insertion loss and crosstalk of the designed AWG were -5.46 dB and -17.2 dB, respectively. The integration of the half Si3N4 AWG and the arrayed Si loop reflectors can effectively reduce the large footprint of a Si3N4 AWG device with a standard complementary metal–oxide–semiconductor process while maintaining a relatively high performance.

Circuit Level Realization of Low Latency Radix-4 Booth Scheme for Parallel Multipliers

A novel radix-4 Booth encoding scheme has been presented in this paper. By means of the modified truth table, the transistor level delay from inputs to the partial products has been reduced to four transistors. Also, the output waveforms are free of glitch due to the utilization of pass-transistor logic. The calculation of propagation delay for the critical path has been provided to show the superior speed performance of the proposed architecture. Based on the simulation results using HSPICE for Taiwan semiconductor manufacturing company 0.18 µm standard complementary metal–oxide–semiconductor process and 1.8 V power supply, a speed improvement of 24% is obtained compared to the previous architectures when the proposed scheme along with the best reported works have been redesigned and simulated in the same technology platform.

High-Speed DD Transmission Using a Silicon Receiver Co-Integrated With a 28-nm CMOS Gain-Tunable Fully-Differential TIA

We report >100-Gb/s direct-detection (DD) transmission using an integrated silicon optical receiver, which comprised a fully-differential 28-nm complementary metal-oxide-semiconductor (CMOS) transimpedance amplifier (TIA) wire-bonded to a Silicon-Germanium (SiGe) balanced photodiode (PD). The fully-differential TIA architecture enabled significant bit-error-rate (BER) and signal-to-noise ratio improvements over a single-output TIA design when introducing it to the DD transmission. We experimentally validated its effectiveness in both back-to-back (B2B) and 2-km long standard single-mode fibre (SSMF) links using 50/100-Gb/s signals, including Nyquist on-off keying (OOK), Nyquist 4-ary pulse amplitude modulation (PAM4), uniformly-loaded DD optical orthogonal frequency division multiplexing (DDO-OFDM) and adaptively-loaded DDO-OFDM. Furthermore, we demonstrate that the integrated optical receiver was capable of balancing the trade-off between its electrical bandwidth and transimpedance gain by simply adjusting a voltage supply to the TIA. Without the need for optical amplification and while keeping the BERs below the 7% forward error correction limit, up to 173.22-Gb/s and 139.86-Gb/s adaptively-loaded DDO-OFDM transmission was achieved for B2B and 2-km transmission, respectively. The demonstrated results highlight the potential of the integrated silicon optical receiver, fabricated using the standard CMOS process for high-speed and short-reach optical interconnects.

A CMOS-MEMS BEOL 2-axis Lorentz-Force Magnetometer with Device-Level Offset Cancellation.

Lorentz-force Microelectromechanical Systems (MEMS) magnetometers have been proposed as a replacement for magnetometers currently used in consumer electronics market. Being MEMS devices, they can be manufactured in the same die as accelerometers and gyroscopes, greatly reducing current solutions volume and costs. However, they still present low sensitivities and large offsets that hinder their performance. In this article, a 2-axis out-of-plane, lateral field sensing, CMOS-MEMS magnetometer designed using the Back-End-Of-Line (BEOL) metal and oxide layers of a standard CMOS (Complementary Metal–Oxide–Semiconductor) process is proposed. As a result, its integration in the same die area, side-by-side, not only with other MEMS devices, but with the readout electronics is possible. A shielding structure is proposed that cancels out the offset frequently reported in this kind of sensors. Full-wafer device characterization has been performed, which provides valuable information on device yield and performance. The proposed device has a minimum yield of with a good uniformity of the resonance frequency kHz, kHz and quality factor , at ambient pressure. Device sensitivity to magnetic field is fAT at Pa when driven with .

Low-Cost Microbolometer Type Infrared Detectors

The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the CMOS-compatible microbolometer IRFPAs in the aspects of the pixel structure, the read-out integrated circuit (ROIC), the focal plane array, and the vacuum packaging.

Broadband high-efficiency triple-tip spot size converter for edge coupling with improved polarization insensitivity

Fiber-to-chip couplers are an essential part of the interfaces to integrated photonic devices, and high coupling efficiency over a broad wavelength range is preferred for most applications. Furthermore, couplers with low polarization dependence are also of great practical significance. While tapered waveguide couplers have been applied to overcome the mode mismatch between waveguides and fibers, the inherent geometric asymmetry of high-index-contrast waveguides, especially for those with a thick core layer, leads to polarization dependence in their performance. Here a triple-tip spot size converter as an edge coupler is proposed to improve the polarization insensitivity and coupling efficiency over a broadband range for either thick or thin waveguides. For both TE and TM polarization, it is shown that our design can have below 1 dB coupling loss over a 600 nm window around 1550 nm wavelength for Si3N4 waveguides of typical core thicknesses. Meanwhile, this kind of coupler also shows better fabrication and assembly tolerance than the traditional single-tip spot size converter (inverse taper coupler). Our proposed device can be easily fabricated in simple fabrication processes compared to other designs and have good compatibility with the standard complementary metal-oxide–semiconductor processes.

A 108 F2/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise

In this paper, we present a fully reconfigurable resistive random access memory (RRAM) physical unclonable function (PUF) based on the truly random dynamic entropy of the ubiquitous jitter noise, which is intrinsically different from most previously demonstrated PUF implementations with semiconductor fabrication’s process variation as the static entropy source. In addition, the proposed RRAM PUF is operated by configuring the mainstream RRAM cells to either high resistance state (for ‘1’) or low resistance state (for ‘0’), according to the customized ring oscillator (RO) true random number generator’s digital output that is determined by the random jitter noise. By completely removing the need of dedicated split resistance circuitry (SRC) in existing RRAM PUFs, the proposed implementation is fully compatible with the SET/RESET operations of the RRAM array for mainstream memory applications, leading to minimized design overhead and enhanced reliability without SRC-caused error bits. Fabricated using 130 nm standard complementary-metal-oxide-semiconductor (CMOS) process plus post-processing dedicated to the RRAM devices, the proposed RRAM PUF cell features an ultra-compact footprint of $1.82~\mu \text{m}^{2}$ (i.e., 108 $F^{2}$ ), which is capable of generating ~107 PUF bits per cell due to the time-variant property of jitter noise and the full reconfigurability of the RRAM PUF. This significantly innovates all the previous weak PUF implementations based on the static entropy source of process variation, where the maximum bit number per PUF cell is always limited and fixed after the chip fabrication. Meanwhile, ultra-low native unstable bits of 0.28% and bit error rate (BER) per 10°C of 0.03% can be achieved for the fabricated RRAM PUF. Moreover, by passing the widely-adopted bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test under various VT conditions, the true randomness of the customized RO TRNG’ dynamic entropy is validated using 65 nm standard CMOS process. Compared with the state-of-the-art weak PUF implementations, the native unstable bits is improved by $5.36\times $ and the BER per 10°C is improved by $4\times $ , even under the widest operating temperature range from −50°C to 150°C.

Easily reproducible top-emitting organic light-emitting devices for microdisplays adapted to aluminum contact from the standard CMOS processes

Organic light-emitting devices (OLEDs) on the silicon backplanes processed via the standard foundry complementary metal–oxide-semiconductor (CMOS) processes were developed with the state-of-the-art electrical doping technology to meet the optical and electrical requirements, resulting in high luminance (over 5000 cd/m2) for the green emissive OLED microdisplay. The unavoidable oxidized aluminium contact after the CMOS processes on the top layer of the pixel was found to significantly increase the driving voltage of the device (up to 1 V at 100 cd/m2 luminance). To aid in the extraction of the accurate device parameters for setting up an equivalent circuit, the reference top-emitting OLEDs without bottom metal contacts were deposited directly on interconnection-metal-only silicon substrates from the CMOS foundry. The distribution of the AlOx of the top-layer metal contact on silicon (the bottom anode of OLEDs) was confirmed by the X-ray photoelectron spectroscopy (XPS) depth profiles.

Integrated Color Photodetectors in 40-nm Standard CMOS Technology

For the further integration of receivers in multi-color visible light communication systems, a novel color photodetector (PD) was designed and fabricated by using a 40 nm standard complementary metal oxide semiconductor (CMOS) process without any process modifications. The PD consists of CMOS photodiode and two-dimensional (2D) polysilicon subwavelength grating above the photodiode. The 2D polysilicon grating is controlled in structural parameters to realize color filtering, based on guided-mode resonance, for the first time in a standard CMOS process. Here three kinds of color PDs were designed to respond to the three primary colors. The measured results demonstrate that the color PDs exhibit wavelength selectivity in the visible range (400-700 nm) and the maximum peaks in the spectral response curves of them are at 660 nm (red), 585 nm (green) and 465 nm (blue), respectively. In addition, the added 2D polysilicon grating almost does not reduce the responsivity of the photodiodes.