Standby Current Research Articles

Graphoepitaxially Side‐By‐Side Nanofins Along Atomic Terraces for Enhancement‐Mode FinFETs with 108 On/Off Ratio

AbstractThe innovation of 3D FinFETs using top‐down silicon nanofins represents a significant advancement toward scaling down microchip process nodes to the cutting‐edge 3‐nm level. While bottom‐up semiconductor nanofins also hold promise as building blocks for FinFETs, their controlled growth remains challenging. Drawing inspiration from the guided roots along brick gaps, this study shows that the aligned atomic terraces on an annealed miscut LaAlO3 surface can trigger an exceptional graphoepitaxial effect, encouraging the bottom‐up vapor‐phase growth of self‐aligned nanostructures such as CdS, CdSe, ZnSe, and ZnTe. Subsequently, the resultant CdS nanofins, characterized by narrow widths of ≈20 nm and large height‐to‐width ratios exceeding 16, can be seamlessly assembled into arrayed FinFETs on the insulating LaAlO3 substrate, obviating the need for post‐growth alignment steps. Unlike most nanostructure‐based planar transistors, which often operate in depletion mode characterized by negative thresholds, these FinFETs operate in enhancement mode with positive thresholds (≈5 V), ≈10−14‐A standby currents, and ≈108 on/off current ratios. The achieved ratio surpasses the record for planar enhancement‐mode CdS transistors by 4 orders of magnitude, primarily due to the enhanced electrostatic control over the nanofins. Overall, the graphoepitaxially side‐by‐side nanofins show tremendous potential to expand the repertoire of FinFETs based on non‐silicon semiconductors.

A high-performance wordline voltage-generating system for low-power low-voltage flash memory

Wordline (WL) voltage-generating system is a crucial block in flash memory. It generates a voltage higher than the supply voltage for reading, programming and erasing in flash memory. However, operation accuracy is deteriorated by the excessive overshoot and ripple voltage. Moreover, current consumption in standby mode shortens the life of memory. The paper presents a high-performance wordline voltage-generating system in 55nm CMOS technology. In active mode, a variable stage and frequency charge pump system is proposed to suppress overshoot and ripple of WL voltage (VWL) when the supply voltage ranges from 1.5V to 2.1V. To cut down standby current, an ultra-low power voltage reference circuit operating in subthreshold region is introduced. When recovering from standby mode, a standby recovery management circuit is utilized to minimize WL voltage setup time. The ripple voltage is 3mV at 30pF load with 20MHz pumping frequency in active mode in post-simulation. The WL voltage setup time when recovery from standby mode is equal to 13.7ns, even though the average standby current is less than 0.98µA typically.

Total ionizing dose radiation hardening technology based on double-charge multiple-step ion implantation

This paper describes the total ionizing dose (TID) radiation hardening of buried oxide in separation by implantation of oxygen silicon on insulator (SOI) substrates. In this study, 0.5-μm partially depleted SOI complementary metal–oxide–semiconductor (CMOS) transistors and circuits were prepared using double-charge multiple-step ion implantation and annealing, and the changes in the drive current, leakage current, and threshold voltage of the CMOS transistor under different TID radiation conditions were compared. Under a TID of 500 k Rad(Si), radiation-hardened H-type N-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <100 mV in the worst case, and H-type P-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <150 mV. Under a TID of 1 Mrad(Si), CMOS transistors showed no significant increase in leakage current caused by TID radiation. Under a TID of 500 k Rad(Si), the standby current of the radiation-hardened 32-bit DSP was <1.5 mA. The high-density integrated circuits prepared using this technology performed well under harsh ionizing radiation environments. Finally, this technology was compared with similar foreign technologies and TID-unhardened wafers with hardened wafers. This technology reached the international advanced level among equivalent technologies regarding hole capture cross section and maximum threshold voltage drift in the model. PACS85.30.De 85.30.-e.

A Detuning-Repeater-Based Dynamic Wireless Charging System With Quasi-Constant Output Power and Reduced Inverter Count

High-density coil installation to achieve a smooth power transfer inevitably increases construction costs, reducing the acceptance of dynamic wireless power transfer (DWPT). In this article, a detuning-repeater-based DWPT system is proposed to provide a relatively constant power at a reduced count of inverters. Half of the inverter-connected transmitter coils in conventional DWPT systems are served as passive repeater coils. The repeater relays the power from the transmitters on both sides to take the role of the main power transfer channel when the receiver is moving towards it. A detuning method is proposed to suppress the standby currents inside the idle repeater coils by utilizing the variation of receiver reflecting impedance during the receiver moving towards/away. An optimization method to achieve less power fluctuation is designed based on the detuning rate. The tradeoff between the power fluctuation and current suppression is analyzed. The system performance against parameter variations is also performed. A 100 W down-sized prototype is developed, and the experimental results show that the proposed DWPT system can achieve a quasi-constant output power with a power fluctuation of 8.5% and a system efficiency of around 82% during the entire dynamic process.

Modelling and Implementation of a Hybrid Renewable Energy System for a Stand-Alone Application

Rapidly developing modern energy systems incorporate significant contributions from renewable sources. The recent adoption of distributed generation sources and microgrids powered by renewable sources such as solar cells, tidal wind, and fuel cells is one of the primary causes of rising global energy demand. Integration of different energy sources into a hybrid system is envisioned as a viable solution for decentralized energy generation. Consequently, this study aims to integrate two energy sources with storage devices to construct a hybrid renewable energy system that will provide reliable electricity for remote and off-grid installations in the Sabon Gida Community of Kaduna State. This will contribute to the attainment of the seventh United Nations Sustainable Development Goal (Affordable and clean energy) (UN). This study utilized the Felicity PV panel. Its cell specifications are as follows: Peak power 175Wp, Open-circuit voltage (VOC) 21.6V, Maximum power current Imp 9.72A, Maximum power voltage Vmp 18V, short-circuits current Isc 10.2A, operating cell temperature Tc 250C, and Ideality factor Am 1.5. For the wind turbine, a model WT-400 with a rated power of 400W, 12V output voltage, and a wind controller with a standby current of 3.6mA, rated at 12/24V auto output voltage were utilized. The maximum power output of the PV energy model based on the specified weather variable was 620watts, whereas the maximum power output of the wind turbine energy model based on the selected wind speed was 301watts. Based on design calculations, the projected load demand for the location under consideration was 304 watts. The prototype was implemented, tested, and validated. The test results indicate that the output power was sufficient to fulfil the load requirements of the chosen location.

Novel Design of a Ternary-CMOS With Vertical-Channel Double-Gate Field-Effect Transistors

A tunneling-based ternary CMOS (T-CMOS) offering a low standby current and fast switching speed is developed using a novel device structure for field-effect transistors (FETs). In the new transistor devices, referred to as vertical-channel double-gate (VCDG)-FETs, a vertical current path from drain to source is formed on the drain, and a body placed below the drain is electrically isolated, except for the tunneling junction appearing at the drain and body interface. At the junction, most of the OFF-state current flows, which is independent of the gate voltage. Furthermore, the OFF-state current can be further reduced to the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−17</sup> A by employing a drain with a retrograded doping profile. In this profile, the channel–drain junction tunneling current, which varies with the gate voltage, is substantially suppressed to less than the body–drain junction tunneling current in the OFF state. In addition, an electrostatic channel controlled using double gates facilitates a small subthreshold swing (SSW) of 65 mV/dec. With p- and n-channel VCDG-FETs, a T-CMOS exhibiting three logic states is developed with a standby current on the order of 1 pA and transfer characteristics with a very narrow transition width.

Effects of cobalt deposition and pretreatment process on electrical properties of products

The preferable conditions for formation of high quality CoSi2 films and effect of process parameters on properties of products were investigated. The pretreatment should not only remove the natural oxide layer completely, but also could not damage Si substrate. The good static random access memory (SRAM) proportion of products is high when pretreatment thickness is 20 Å, reached 96.5%. The radio frequency (RF) bias power process parameter should also take an optimal value. When RF bias power is 150 W, the good SRAM proportion of products is greater than 98%. The 100 Å Co can just completely react with Si substrate after twice annealing (500 °C 30 s and 750 °C 30 s), and if it exceeds 100 Å, Co will be residual. Decreasing Co thickness leads to contact resistance (RC) increase whatever in N-well or P-well. The overall standby current (Isb) of product is least when Co thickness is 80 Å. Finally, the products achieved good electrical properties when Co thickness is 80 Å, pretreatment thickness is 20 Å and RF bias power is 150 W.

Self-Sustainable Long-Range Backscattering Communication Using RF Energy Harvesting

Radio-frequency (RF)-powered backscattering communication (BC) has many advantages, such as low-power consumption, battery-free, small size, low cost, full sealing, manual maintenance-free, and easy mass deployment. However, the weak RF energy harvested and the short BC distance have become the two critical obstacles in the real-world implementation of this potential technology. In this article, we propose a high-sensitivity RF energy harvesting (RFEH) and long-distance BC method, and for the first time, we demonstrate the RF-powered self-sustainable long-distance BC device named RFEH LoRa. In order to improve RFEH sensitivity, an ultralow-power (ULP) consumption voltage monitoring and startup control circuit topology is designed to reduce the power consumption to 245 nanowatt (nW) during the accumulation of RF energy. While in order to increase the BC distance, a direct digital frequency synthesis technology is used to generate a linear frequency modulation square wave sequence conforming to the LoRa specifications based on the ULP microcontroller unit, and the square wave is used to drive an RF switch to achieve long-distance BC of hundreds of meters. Test results show that the instantaneous BC current is as low as 130 microampere ( μA), and the standby current is only 52 nanoampere (nA). RFEH LoRa is implemented with commercial off-the-shelf components. It can self-startup by harvesting RF energy as low as -22.5 dBm, and send its sensing data to the receiver of 381-m away.

High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

High-Sensitivity Hydrogen Sensor Based on AlGaN/GaN Heterojunction Field-Effect Transistor.

We have developed a Pd-functionalized hydrogen gas sensor based on a recessed AlGaN/GaN heterostructure field-effect transistor. The AlGaN barrier layer under the Pd catalyst was partially etched to enhance its sensitivity. Both low-power consumption and high sensitivity were achieved by employing a recessed structure. Sensor characterization was carried out at the temperature range from room temperature to 250 °C, among which the best sensing characteristics were observed at 200 °C. A sensitivity of 380% with a response time of 0.25 s was achieved at a bias voltage of 0.3 V at 200 °C under a hydrogen exposure concentration of 4%. The standby power consumption was only 2 μW for the sensing area of 100×28 μm² due to the low standby current, which was caused by the recessed AlGaN barrier layer.

Ultra‐low power micro Wi‐Fi scattering communication device

A Wi-Fi scatter communication method based on microcontroller unit (MCU) is proposed, and an ultra-low power micro Wi-Fi scatter communication device μWi-Fi is designed and implemented. First, according to the characteristics of the microcontroller, the software virtual modulation method and the serial communication port direct memory access (DMA) transmission method is proposed to realise Wi-Fi scattering communication. Then the MCU + exclusive OR (XOR) baseband architecture is proposed to further reduce the main frequency of the microcontroller and the system power consumption. The communication test and power consumption measurement results show that μWi-Fi can generate signals conforming to the IEEE802.11b standard, which can be received and forwarded by universal Wi-Fi routers. Its effective communication distance reaches 15 m, its communication peak current reaches 720 μA, and its standby current reaches 390 nA. Compared with traditional internet of things (IOTs) Wi-Fi devices, μWi-Fi can not only reduce the power consumption of Wi-Fi communication by 2–3 orders but also has a simple composition and low cost, which is very helpful for the rapid development of Wi-Fi IoT products.

전류 피크를 낮춘 SSPA 펄스변조 바이어스 회로 설계

This paper investigates pulse modulator bias circuit design for the drain of solid-state power amplifier with low peak charging current of capacitor banks. By using an inductor between a voltage regulator and the capacitor banks in the pulse modulator bias circuit, the charging time is delayed and current peak is reduced. The current charging characteristics corresponding to the inductance and DC resistance of the inductor are analyzed based on the damping time constant and oscillation frequency. Bounds of damping time constant and oscillation frequency are set for the capacitor banks to be charged by specified time periods for a maximum pulse repetition frequency of 2,600 Hz. Simulation results show that the current peak is significantly reduced by the inductor, and the current charging characteristics are similar to the analysis. The ratio of current peak and mean excluding stand-by current of a prototype without inductor is 10.0 A/A, while that of a prototype with inductors is enhanced to 2.3 A/A with an appropriate charging delay.

A 7T-SRAM With Data-Write Technique by Capacitive Coupling

A 7-transistor static random access memory (SRAM), in which cell data are written by capacitive coupling, is proposed. In the 7T-SRAM configuration, the traditional read/write port using two pass-gates (PGs), which are used in 6T-SRAM, is eliminated and the read port using two transistors such as 8T-SRAM and the equalizer for the cell node pair are installed. This read port transistor also acts as a coupling capacitor for writing external data after floating paired cell nodes. The elimination of current-drive via PGs in read/write operation solves current-conflict problems. No degradation of static noise margin (SNM) reduces V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> minimum by 0.1 V in 24-nm 3.3-V high-voltage CMOS process and by 0.3 V in 40-nm standard logic CMOS process. A large coupling transistor design enhances differential cell signal in write, and enables stable operation for scaled SRAMs with large threshold voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> variation. A 7T-SRAM cell size is comparable to that of 6T-SRAM in 24-nm 3.3-V high-voltage CMOS process and 10% smaller than that of 8T-SRAM in 40-nm standard logic CMOS process. A prototype of 64-b 7T-SRAM with 8.74 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell size using 24-nm 3.3-V high-voltage CMOS process has been demonstrated for resistive nonvolatile RAM (NVRAM) page buffer application. The 7T-SRAM macro has achieved 20-ns/10-ns cycle time and 18-ns/10-ns access time at 1.5 V/1.8 V V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> , and also has realized 100% macro yield in a wafer and low soft error rate (SER) of 400 FIT/Mb at 1.6-V V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> minimum, which is equal to |V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tp</sub> | + |V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tn</sub> | for 0.1-μA low standby current.

Total ionizing dose effects of &lt;b&gt;γ&lt;/b&gt; and X-rays on 55 nm silicon-oxide-nitride-oxide-silicon single flash memory cell

The total ionizing dose (TID) effects on 55 nm SONOS flash cell, caused by &lt;sup&gt;60&lt;/sup&gt;Co-γ ray and 10 keV X-ray radiation source, are systematically investigated in this paper. The degradation of electrical characteristics is discussed while the underlying physical mechanism is analyzed. The drift of &lt;i&gt;I-V&lt;/i&gt; characteristic curve, the degradation of memory window, and the increase of stand-by current are observed after TID irradiation separately by the two radiation sources. The data retention capability is also affected by the TID irradiation. The &lt;i&gt;I&lt;/i&gt;-&lt;i&gt;V&lt;/i&gt;&lt;sub&gt;g&lt;/sub&gt; curve of the programmed single flash cell significantly drifts towards the negative direction after TID irradiation, while the negative drift of erased state is much slower. Referring to the erased state, the drift directions of &lt;i&gt;I&lt;/i&gt;&lt;sub&gt;d&lt;/sub&gt;-&lt;i&gt;V&lt;/i&gt;&lt;sub&gt;g&lt;/sub&gt; curves for γ- and X-ray radiation source are obviously different. The physical mechanism of irradiation damage in a 55 nm SONOS single flash cell is discussed in detail by the energy band theory and TCAD simulations. The storage charge loss in silicon nitride layer, the charge accumulation, and the generation of interface states all together lead to the degradation of threshold voltage and stand-by current after TID irradiation. Another cause for the increase of stand-by current is the positive trapped charges in the isolated oxide induced by irradiation, which leads to the generation of leakage paths. Significant dose enhancement effect of X-ray irradiation is observed in this paper. Device model of memory transistor c is established while the dose enhancement effect of X-rays is investigated by Geant 4 tool. The high-&lt;i&gt;Z &lt;/i&gt;materials above the poly-silicon gate lead to the dose enhancement effect of X-rays’ irradiation, which results in the higher degradation. The density of electron-hole pairs produced by irradiation in W layer is much higher than in Cu layer. In particular, W layer is a critical factor regardless of the thickness, which can be obviously observed in the simulation.

Total ionizing dose effect of ferroelectric random access memory under Co-60 gamma rays and electrons

Ferroelectric random access memory (FeRAM) has superior features such as low power consumption, short write access time, low voltage, high tolerance to radiation. Data about the total ionizing dose (TID) radiation effects of FeRAM have not been rich in the literature so far. Experimental study of the ionizing radiation effect of FeRAM is carried out based on Co-60 γ rays and 2 MeV electrons. And the TID radiation damages to the FeRAM in the dynamic biased, static biased and unbiased case are studied. The direct current and alternating current parameters are tested by J-750. The test results indicate that the stored information about the memory cell has no change before failure, the ferroelectric capacitors are still able to hold the data. Accordingly, the TID failure of the FeRAM should be mainly ascribed to the poor TID hardness of the peripheral complementary metal oxide semiconductor circuits. Besides, three types of electric fields from three working conditions can result in different generation and recombination rates of electronhole pairs. For static biased case, the internal electric field in the FeRAM is constant. It can lead to high net production of the electronhole pairs and a great number of trapped charges. Hence the radiation damage in the static biased case is most serious. With the increase of the total radiation dose, the electrical parameters of FeRAM have different degradations. Part of the parameters that can be detected by J-750, may lapse before they are detected online. Standby current, operating power supply current, leakage current and output low voltage are radiationsensitive parameters of FeRAM through analyzing the test data. And, other parameters, which have slight changes, have small effect on the degradation of the device. Furthermore, the electron accelerator is used in electron irradiation experiment. By comparing the results of the two kinds of radiation tests, it is discovered that the electrons tend to cause lighter TID degradation than Co-60 γ rays because of the high density of electrons in the electron irradiation environment and low net production rate of electronhole pairs. In addition, the electrons have weaker penetration than Co-60 γ rays due to low energy. The device packaging, the upper metal layers can also influence the experimental result of electron irradiation. The above conclusions provide a reference value for the total dose effect of FeRAM and will be of great significance for studying the radiation hardening of FeRAM.

The improvement of HEIP immunity using STI engineering at DRAM

The increase of standby current of DRAM caused by the HEIP degradation of p-MOSFET and the way to improve the HEIP immunity without the deterioration of performance are reported. The electron trapping at the top region of STI SiN liner is the main cause of the HEIP degradation. To improve the HEIP immunity, several candidates are examined. The large tabbed-gate device and the thicker STI sidewall oxide are not proper for DRAM due to the decreases of Ion and the refresh time, respectively. The thin poly Si liner, which is inserted between the STI sidewall oxide and the SiN liner, acts as an immune layer against the HEIP degradation. So, the poly Si liner scheme can be a good solution to improve the HEIP immunity without the deterioration of DRAM performance.

A 0.5-V all-digital clock-deskew buffer with I/Q phase outputs

This paper proposes a low supply voltage all-digital clock-deskew buffer with in-phase and quadrature phase (I/Q) outputs on an intra-chip. In some application-specific integrated chips or silicon intellectual properties might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, I/Q clock signals are widely adopted in the communication systems and double data rate memories. The proposed all-digital clock-deskew buffer can operate from 220 to 570 MHz at 0.5 V and the power consumption is 1.95 mW at 570 MHz. This buffer can also supply a quadrature phase output using a proposed two-step edge detector.

Ultra‐low leakage SRAM design with sub‐32 nm tunnel FETs for low standby power applications

Tunnel-field-effect transistors (TFETs) operate by quantum band-to-band tunnelling and display a steeper subthreshold slope than MOSFETs which substantially diminishes the standby current. This work explores the TFET-based SRAM utilisation for Low STandby Power applications. An 8 T TFET SRAM cell operating at V-DD = 1 V, which, in contrast to other 6 T TFET SRAMs, is write-disturb- and half-selection-free is proposed. Simulations based on 30 nm p- and n-TFETs models relying on I-D, C-GS, C-GD vs. V-GS, and V-DS look-up tables extracted from TCAD, indicate that the proposed cell has a Read SNM and a Write SNM of 120 and 200 mV, respectively, which are well above state of the art values repotted in the literature. When utilised in an 128 x 128-bit memory array the proposed cell enables read and write operation at 3.84 GHz and 806 MHz, respectively, and a cell leakage of less than 2fA/bit, which makes it an excellent choice for Internet of Things applications.

A Nanocurrent Power Management IC for Low-Voltage Energy Harvesting Sources

This paper presents the nanopower design of an integrated 1-μW-to-5-mW power management circuit. The circuit integrates a boost converter with maximum power point tracking, a low drop-out voltage regulator (LDO), and a start-up circuit for battery-less activation from discharged states. The IC implements a dynamic two-way power routing policy that ensures a fast start-up from discharged states even with very large energy storage capacitors. In order to reduce the intrinsic power, asynchronous control logic was adopted. The circuit was implemented in a STMicroelectronics 0.32-μm microelectronic technology. The power conversion section and the LDO draw, respectively, stand-by currents of 121 and 414 nA in the active modes. The circuit achieves a peak conversion efficiency of 77.1% and a minimum start-up voltage of 223 mV.

CMOS Sensor Nodes with Sub-PicoWatt TFET Memory

This paper describes the applicability of tunnel FETs (TFET) to ultra-low-power sensor-node embedded static random-access memories (SRAMs). Numerical TCAD device simulations were used first to characterize and optimize the performance of the TFET. The optimized TFETs show a steeper subthreshold slope than CMOS leading to a five orders of magnitude reduction in standby current. A lookup table model for circuit simulation of the TFET was developed based on characteristics obtained from TCAD simulations. A TFET SRAM cell is proposed and its performance is analyzed. Our novel 8T TFET SRAM cell operates at $V_{\mathrm{ DD}}=1$ V or lower. The read and write static noise margins are evaluated at 120 and 200 mV, with the operation speeds of 3.8 GHz and 800 MHz at $V_{\mathrm{ DD}}=1$ V in read and write, respectively. The cell leakage is less than 5 fA at $V_{\mathrm{ DD}}=1$ V. A sensor node architecture for implementation in a hybrid CMOS/TFET process with a large memory is proposed where the memory consumes as little as 4 fW/cell or 4.1 pW for a 1-kb array at 1 V supply voltage.