Novel Design of a Ternary-CMOS With Vertical-Channel Double-Gate Field-Effect Transistors

Abstract

A tunneling-based ternary CMOS (T-CMOS) offering a low standby current and fast switching speed is developed using a novel device structure for field-effect transistors (FETs). In the new transistor devices, referred to as vertical-channel double-gate (VCDG)-FETs, a vertical current path from drain to source is formed on the drain, and a body placed below the drain is electrically isolated, except for the tunneling junction appearing at the drain and body interface. At the junction, most of the OFF-state current flows, which is independent of the gate voltage. Furthermore, the OFF-state current can be further reduced to the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−17</sup> A by employing a drain with a retrograded doping profile. In this profile, the channel–drain junction tunneling current, which varies with the gate voltage, is substantially suppressed to less than the body–drain junction tunneling current in the OFF state. In addition, an electrostatic channel controlled using double gates facilitates a small subthreshold swing (SSW) of 65 mV/dec. With p- and n-channel VCDG-FETs, a T-CMOS exhibiting three logic states is developed with a standby current on the order of 1 pA and transfer characteristics with a very narrow transition width.