Beyond 3 nm node, the transistor architecture of stacked channel gate-all-around (GAA) FETs can replace FinFETs for advanced technology node due to the improvement of power, performance, and area by the enhanced short channel control, design flexibility, and drive current per footprint. High ION and small parasitic RC are the keys to extend nanosheet technologies for N+1 and N+2 nodes. To extend nanosheets to next nodes, we have demonstrated additional enabling knobs such as high mobility channels, high-k gate dielectrics, and highly stacked channels to effectively increase the ION for high performance. Beyond stacked nanosheets, new transistor architectures such as TreeFET (a combination of FinFET and stacked nanosheets) and CFET (3D stacked n and p FETs) can further enable cell height scaling. CFETs and atomic channels have potentials to be used in A5 and A2 nodes according to the transistor roadmap by IMEC [1], respectively. Note that ultrathin body as thin as 1 nm can be considered as atomic channels for nearly ideal SS and high ION/IOFF for low power application.First of all, high mobility channel material is the key factor to improve performance CV/I. As a result, Ge/GeSi and GeSn are the target high mobility channels for nFETs and pFETs, respectively. For nFETs, Ge is an attractive option for high mobility channel to boost the ION thanks to its higher electron mobility than Si [2]. For pFETs, strained GeSn has higher hole mobility than Ge to improve the ION for pFETs due to the hole effective mass reduction under compressive strain [3]. For a fixed footprint, the vertically highly stacked GAA channels can provide large ION to achieve high performance and area scaling for advanced technology node.In addition to high mobility channel, the performance of GAAFET can be improved by scaling down gate oxide thickness. However, the gate leakage problem increases with scaling down the gate oxide thickness. As a result, high-k materials were proposed as gate oxide for gate leakage reduction and performance enhancement in GAAFETs. Plasma-enhanced atomic layer deposition (PEALD) HfxZryO2 was reported to achieve high-k value by optimizing the Hf and Zr content [4], respectively. In this work, a high k value of 47 is achieved in Hf0.2Zr0.8O2 alloy. Furthermore, the high-k gate dielectrics is integrated into stacked GAAFETs successfully.However, the challenge of Ge-based channel is the large IOFF due to the small bandgap [5-7]. Ultrathin body device can effectively reduce the IOFF, but the mobility degradation is observed as the channel thickness decreases below 5nm due to surface roughness scattering. Moreover, the high mobility GeSn can afford some mobility loss due to the ultrathin body [8]. Furthermore, the ION can be further improved by channel stacking with the suppression of IOFF by the ultrathin body.For Si nanosheets, the mismatch between hole mobility and electron mobility in nanosheets [9] might lead to potential design challenges of CMOS. As a result, the TreeFET transistor architecture combining with FinFETs and stacked nanosheets is proposed [10] and experimentally demonstrated [11] as a candidate beyond nanosheets. TreeFETs with {100} surfaces can enhance the electron mobility of Si, while {110} sidewalls are beneficial to hole mobility for both Si and Ge. TreeFETs with additional fin interbridges (IB) between nanosheets can increase Weff and enhance ION per footprint for high-performance devices beyond FinFETs and stacked nanosheets.3D transistor stacking can enable further cell height scaling and extend Moore's law scaling. The pFET and nFET are able to fold on each other to reduce 50% of inverter cell area ideally in CFET [12, 13], as a promising transistor architecture beyond stacked nanosheets. As compared to the sequential 3D process, no wafer bonding or layer transfer is required in the monolithic 3D process. Moreover, monolithic 3D by epitaxy can reduce the FEOL cost and the parasitic RC as compared to sequential 3D. The high mobility channel material of GeSi is used for CFET demonstration in this work [14]. Heavily doped sacrificial layers are beneficial for S/D resistance reduction by thermal annealing during the device fabrication. Reportedly, dielectric layers in S/D regions are used for the electrical isolation between n/p FETs in CFET structure [15], but the complicated S/D recess and dual S/D selective epi regrowth are required. In this work, a simple process without S/D selective epi regrowth can achieve self-aligned CFETs with multiple P/N junction isolation to effectively reduce the leakage current. Acknowledgements- This work is supported by National Science and Technology Council (111-2218-E-002-040-MBK, 111-2634-F-A49-008-, and 111-2622-8-002-001-), Ministry of Education (NTU-CC-112L890901), and Taiwan Semiconductor Research Institute (TSRI), Taiwan. Figure 1
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Aug 12, 2024
Mengying Long + 6
Open Access