Stacked Capacitor Structure Research Articles

Direct-Write Laser Greyscale Lithography for Multi-Layer Lead Zirconate Titanate Thin Films.

Direct-write laser greyscale lithography has been used to facilitate a single step patterning technique for multi-layer lead zirconate titanate (PZT) thin films. A 2.55 μm thick photoresist was patterned with a direct-write laser. The intensity of the laser was varied to create both tiered and sloped structures that are subsequently transferred into multi-layer PZT(52/48) stacks using a single Ar ion mill etch. Traditional processing requires a separate photolithography step and an ion mill etch for each layer of the substrate, which can be costly and time consuming. The novel process allows access to buried electrode layers in the multi-layer stack in a single photolithography step. The greyscale process was demonstrated on three 150 mm diameter Si substrates configured with a 0.5 μm thick SiO2 elastic layer, a base electrode of Pt/TiO2, and a stack of four PZT(52/48) thin films of either 0.25 μm thickness per layer or 0.50 μm thickness per layer, and using either Pt or IrO2 electrodes above and below each layer. Stacked capacitor structures were patterned and results will be reported on the ferroelectric and electromechanical properties using various wiring configurations and compared to comparable single layer PZT configurations.

Integration of a Passive-Type UHF RFID Tag Using Ferroelectric Memory Technology

We investigated a passive-type rewritable radio-frequency identification (RFID) tag operating at the UHF (860 – 960 MHz) band and using ferroelectric memory (FeRAM) technology. The transponder integrated circuit(IC) for the UHF RFID tag was implemented with 0.25-μm one-poly four-metal standard logic CMOS technology with the addition of a FeRAM and Schottky diodes. The Pb(Zr,Ti)O3(PZT) capacitor array with a unit area of 1.4 × 1.4 μm for the FeRAM-embedded RFID tag showed a remnant polarization of 30 μC/cm and a leakage current of 1 × 10−5 A/cm at 3 V after full process integration. The novel ferroelectric technology utilizing a stacked capacitor structure and a high capacitance PZT capacitor allowed a highly competitive transponder chip size (550 × 550 μm) by reducing the area of the analogue circuit without adding any complexity to the process integration. The PZT capacitor-based analogue circuitry showed almost the same performance as that of conventional capacitor type circuitry. Thus, the ferroelectric memory technology is very promising for the realization of a cost-effective, passive-type, rewritable UHF RFID tag.

A FERROELECTRIC BASED PASSIVE RFID TAG FOR UHF (860–960 MHz) BAND

ABSTRACT For a longer working distance between passive tags and the reader, the ferroelectric based technologies are proposed in UHF (860–960 MHz) band transponder. The small ferroelectric capacitor layout area with a stacked capacitor structure over circuit region and a large dielectric permittivity of 250 to 500 and small 1T1C cell array layout area with simple 2T2C based reference scheme allow small chip size. The low operation voltage of 1.5 V to 2.0 V without high voltage boosting scheme also contribute to small power consumption and low cost.

Reversible Resistive Switching in Bi4Ti3O12 Thin Films Deposited by Electron Cyclotron Resonance Sputtering

We have newly found that reversible resistive switching occurs at room temperature in a Bi4Ti3O12 thin film deposited by electron cyclotron resonance sputtering. The resistive switching was observed in several stacked capacitor structures regardless of the combination of top and bottom electrodes, such as Au, Pt/Ti, and Ru, though the details of current–voltage characteristics were slightly different. The large magnitude of the resistance ratio in low-resistance and high-resistance states, reversible switching with voltage pulses, and long-term retention characteristics are described. Resistance in the low-resistance state hardly depended on neither the area of the electrode pad nor the thickness of bismuth titanate films. We speculate that reversible resistive switching is caused by the creation and annihilation of a conducting path.

L‐3: Late‐News Paper: A 0.9″ XGA Temperature Poly‐Si TFT LCLV with Stacked Storage Capacitor

AbstractA 0.9” XGA liquid crystal light valve with low temperature Poly‐Si TFT has been developed by using a stacked capacitor structure. The stacked capacitor structure could reduce storage capacitor area because most of the capacitor area is located above the pixel components, such as bus‐lines and TFTs. Therefore, this structure could obtain the required storage capacitance without decreasing aperture ratio. A high aperture ratio of 65% and a high contrast ratio of over 500:1 have been achieved with the fabricated light valve.

(Ba,Sr)TiO3 dielectrics for future stacked- capacitor DRAM

Thin films of barium-strontium titanate (Ba,Sr)TiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> (BSTO) have been investigated for use as a capacitor dielectric for future generations of dynamic random-access memory (DRAM). This paper describes progress made in the preparation of BSTO films by liquid-source metal-organic chemical vapor deposition (LS-MOCVD) and the issues related to integrating films of BSTO into a DRAM capacitor. Films of BSTO deposited on planar Pt electrodes meet the electrical requirements needed for future DRAM. The specific capacitance and charge loss are found to be strongly dependent on the details of the BSTO deposition, the choice of the lower electrode structure, the microstructure of the BSTO, the post-electrode thermal treatments, BSTO dopants, and thin-film stress. Films of BSTO deposited on patterned Pt electrodes with a feature size of 0.2 µm are found to have degraded properties compared to films on large planar structures, but functional bits have been achieved on a DRAM test site at 0.20-µm ground rules. Mechanisms influencing specific capacitance and charge loss of BSTO films are described, as are therequirements for the electrode and barrier materials used in stacked-capacitor structures, with emphasis given to the properties of the Pt/TaSi(N) electrode/barrier system. Major problems requiring additional investigation are outlined.

High Temperature Barrier Electrode Technology for High Density Ferroelectric Memories with Stacked Capacitor Structure

This paper describes the novel stacked electrode structure, , applicable to stacked memory cells in advanced ferroelectric memories. This structure acts as a stable bottom electrode and a barrier on a polysilicon plug up to 700°C and a stable contact resistance of 1.5 KΩ is obtained at the contact size of 0.6 μm. In addition to the low leakage current of lead zirconate titanate ] capacitor (10−8 A/cm2 at 3 V), degradation properties of fatigue and imprint are improved compared with conventional Pt electrodes. The decrease of the switched charge is restricted to less than 10% after the fatigue cycle of 1011. These results indicate its promise as a barrier electrode structure for advanced ferroelectric memory integration.

A gbit-scale dram stacked capacitor with ECR MOCVD SrTiO3 over RIE patterned RuO2/TiN storage nodes

Abstract The capacitor requirements for Gbit-scale DRAMs are discussed in detail. The choice of SrTiO3 thin films over a stacked RuO2/TiN structure for the 1 Gbit DRAM is explained, and particular emphasis is put on the necessity of a stacked capacitor structure and on the selection of a suitable electrode material. The influence of film composition, film thickness and substrate temperature on the properties of ECR MOCVD SrTiO3 films is then presented. Maximum permittivity and low leakage current density were obtained for stoichiometric composition, Sr/Ti = 1·0. A thickness of at least 400 A was found to be necessary to obtain SrTiO3 films with sufficient electrical properties. A substrate temperature of 450°C was found to be a suitable temperature for direct deposition of crystallized SrTiO3 and no degradation of the RuO2/TiN bottom electrode structure. A new reactive ion etching process was developed to pattern RuO2/TiN nodes. The key characteristics of this process are the use of an SOG mask, the choic...

The Novel Capacitor Structure with Polysilicon Grain Hole for Advanced Dynamic Random Access Memory

A simple and new technique to realize relatively large capacitance for high density dynamic random access memory (DRAM) is discussed. This technique adopts the surface modulation technology on bottom electrode polysilicon of stacked capacitor structure, and holes are created in the bottom polysilicon grains. The grain holes are achieved by reactive ion etching (RIE) using the oxide at the grain boundary as etch mask. The capacitance can be increased up to four times, while keeping the leakage current comparable to that of conventional stacked capacitors.

Tunnel Structured Stacked Capacitor Cell (TSSC) with High Reliability for 64 Mbit dRAMs and Formation of Oxide-Nitride-Oxide Film (ONO) on 3-dimensionally (3d) Storage Electrode

We developed a new 3-dimensionally(3d) stacked capacitor structure, a tunnel structured stacked capacitor cell (TSSC), for 64Mbit dRAMs. The TSSC with 2 tunnels realized improved reliability the same as that of the conventional stacked capacitor (STC) and a capacitance of 29 fF with a capacitor height of 0.25 µm because of side-wall electrode formation. The equivalent thickness of SiO2 for the oxide nitride oxide (ONO) is 7.8 nm, and the cell area is 1.8 µm2. The uniformity of the ONO inside the tunnel of the TSSC was confirmed except for the corner of the tunnel, while the thickness of the ONO is slightly greater at the corner. At the corner, the top oxide film of the ONO is slightly thicker than that at the other areas, and accordingly, the shape of the plate electrode at the corner becomes round. These shape effects lead to no generation of the local field concentration at the corner inside the tunnel. They are applied to the other 3d stacked capacitors which have generally been proposed.

A new cell structure with a spread source/drain (SSD) MOSFET and a cylindrical capacitor for 64-Mb DRAM's

A new cell structure for realizing a small memory cell size has been developed for 64-Mb dynamic RAMs (DRAMs). The source/drain regions of a switching transistor are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over gate and field regions, the bitline contact can overlap the gate and field regions. The shallow source/drain junction by the raised source/drain structure realizes a reduction of gate length and isolation spacing. As a result, the DRAM memory cell area can be reduced to 37% of that using the conventional LDD MOSFET. In the fabrication of an experimental DRAM cell, a new stacked capacitor structure has been introduced to maintain enough storage capacitance, even in the small-cell area. The new capacitor is made by a simple and unique process using a cylindrical silicon-nitride sidewall layer. It has been verified that this cell structure has the potential to realize multimegabit DRAMs, such as 64-Mb DRAMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>