Stack Concept Research Articles

Enterprise Integration as a Driving Factor for Guiding Digitalization in a Manufacturing Small and Medium Enterprise

In the face of rapid technological advancements and evolving consumer demands, businesses increasingly turn to digitalization to remain competitive and redefine industry standards. This article delves into the crucial role of enterprise integration within the context of digital transformation, with a specific focus on manufacturing Small and Medium Enterprises (SMEs). Based on fieldwork within the Innovation Factory North project in Denmark, the study presents a three-dimensional framework – architecture, capabilities, and governance – that is instrumental in guiding manufacturing SMEs through the complexities of digitalization. The architecture dimension explores the dichotomy between monolithic and fog (edge) architectures, highlighting their respective merits and challenges. The capabilities dimension introduces the concept of operational capability stacking, demonstrating how specific information systems, when integrated, yield new capabilities. A list of common capabilities in manufacturing enterprises is provided, offering inspiration for manufacturing SMEs to enhance their operational efficiency. The governance dimension injects a strategic dimension into the digitalization process, emphasizing the need for a balanced approach between technology-driven and process-driven optimization methodologies. The research underscores the strategic nature of digitalization in manufacturing SMEs, recognizing the interconnectedness of architecture, capabilities, and governance in achieving sustained success in the digital landscape. The proposed three-dimensional framework is substantiated through real-world applications within Denmark’s Innovation Factory North project, providing tangible insights and scenarios to navigate the intricacies of the digital landscape effectively.

Kinematics-driven design of reconfigurable bistable hinges with high stiffness and stability

Composite tape springs are curved shells with the ability to assume two energetically stable states. By carefully selecting layup and mold during manufacturing, these structures can store significant strain energy, making them ideal for deployable systems. Yet, their potential as reversible reconfigurable structures, particularly as adaptive hinges, remains largely unexplored. In structural applications, both stable states of these hinges must exhibit high stiffness to support loads while retaining the capacity for reversible reconfiguration. This paper introduces kinematics-based stacking concepts aimed at enhancing the stiffness of bistable hinges in both states, allowing for specific fold angles without compromising compliance. These designs leverage snap-through kinematics, resulting in unique architectures with customizable stiffness and stability. Additionally, the paper presents a novel energy-based semi-analytical approach for analyzing the stacking concepts. This approach involves constrained exploration of the energy landscape to assess the design space in terms of stiffness and energy barriers. Through comprehensive parametric studies, the research demonstrates significantly increased stiffness and reduced peak stresses compared to single tape spring designs. This research highlights the potential of employing tape springs as reconfigurable load-bearing structures in diverse applications, including precise adjustments of low-mass payloads like solar panels or antennas on space structures.

A facile and economical approach to fabricate a single-piece bipolar plate for PEM electrolyzers

Water electrolysis will be an essential element of the future energy system, with hydrogen serving as a climate-friendly energy storage medium. To make electrolyzers suitable for market penetration at scale, the cost of manufacturing megawatt electrolyzers must be minimized, with no detrimental effects to their performance and lifetime. Here we show a facile and cost-effective manufacturing method to produce one-piece Ti-based bipolar plates. Low-cost and commercially and readily available feedstock materials (blank sheets, expanded metals and nonwovens) are positively joined using an innovative welding process, diffusion bonding. This approach reduces the contact resistances that can occur with multi-part bipolar plates by around 75%, reducing the number of components and therefore significantly simplifying stack assembly. Ex-situ tests on the contact pressure distribution on the active cell surface reveal a homogeneous pattern with values of about 3.75 MPa ( ± 1.25 MPa). In a first proof-of-concept, a five-cell short stack with a 100 cm2 active cell area, average cell voltages of 1.71 V at 2 A cm−2 could be achieved using our new stack concept.

The Keepers of the Books

The Keepers of the Books Alice-Catherine Carls (bio) Click for larger view View full resolution I GENERALLY DISTRUST social media, but scrolling through the pages of Instagram offers unexpected musings. Between royalty displays, daredevil feats, and wildlife postings, opulent and dilapidated interiors of castles and villas remind us of the vanity of all things. The photographs of French designer-turned-advertiser Francis Meslet show abandoned libraries while others showcase stately British libraries. Surfing the internet further reveals hundreds of pictures of dilapidated or abandoned libraries and entire warehouses filled with discarded books. Fortunately, throughout history, for every book destroyed, one has been saved, and for every intentional or nonintentional, commercial or accidental destruction of books, there has been a loving devotion to preserve the written word. We must never lose sight of this cycle of book production and destruction. Some book-saving initiatives are respectful of form, content, and use, and some change one or all. After one century of mass production revolutionized the volume, cycle, price, and lifespan of book production, the digital revolution has opened endless possibilities. From selling used or discarded books online to creating worldwide digital book archives, a revolution in attitude has occurred. Reverence for physical copies is out, playful initiatives are in. Adding artistic or whimsical elements and deconstructing books give another visual dimension to the [End Page 66] written word and multiply the ways in which it can be seen and read, understood and used. We have come a long way from the early repurposing of leather spines, gold lettering, and gilded pages stuffed with empty blocks filling nouveau riche bookshelves. A modern reverse ekphrasis is repurposing book form and content with bewildering creativity. From DIY enthusiasts to renowned artists, aesthetic surgery repurposes pages into paper cups, saucers, wall art, or containers for flora sculptures. Laurent Niclot and Kailee Bosch's teapots made of laminated book pages pressed between turned wood pieces inspire a new reflection on the term "vessels of knowledge." UK-based Maisie Matilda draws gorgeous paintings on the edges of hardcover books, creating "magical-feeling settings" for the books. Isobelle Ouzman creates altered book sculptures from hardback novels, journals, and notebooks, creating "a mix of illustrated and carved sculptures" with dreamlike visual scenes, prolonging the storytelling in a fairytale genre. New York-based artist Brian Dettmer cuts into old books to create remixed works of art, carving around whatever he finds interesting. LA-based Mike Stilkey uses stacks of old books as his canvases to make small portraits and giant sculptural installations, and often paints in the margins of books. A spectacular version of the book stack concept is Matej Kren's Idiom book tower. This trend was even featured on the front page of the American Historical Association's February 2023 Perspectives. There is a lot to learn from giving books and readers a second chance to rethink literacy. The proliferation of multispatial, multiuse books raises a question, however: Will future generations no longer know how to turn pages (in the way prescribed by their native traditions), the way they no longer know how to read time on analog watches? Will the digital age find an Esperanto format for books? Turning to the "real" preservation of books, everyone can name private or state foundations with unique collections, from the Mazarin Library in Paris to Thomas Jefferson's Monticello; everyone has a favorite antiquarian bookstore or knows private book collectors, from the proud owners of priceless ancient copies to the managers of more democratic collections, such as Alberto Manguel. But these are local and have limited circulation. The real book preservation today is digital and global. UNESCO's World Book Capital Network, launched digitally in the fall of 2022, is committed to encouraging literacy, lifelong learning, and freedom of expression. A collaborative project with worldwide partner organizations created the World Digital Library to which all major national libraries have access. Its descriptive metadata of world libraries' holdings is available in seven languages including English. It features prominently on the home page of the Library of Congress and includes downloadable maps, texts, photographs, movies, and music as well as conference videos, podcasts, and museum artifacts and exhibits. Several bookstores such...

Anatomy of On-Chip Memory Hardware Fault Effects Across the Layers

Reliability evaluation of a microprocessor design may reveal vulnerable silicon areas that require protection against faults, but also hardware structures that are inherently more resilient to faults. In this work, we revisit the concept of system vulnerability stack by analyzing the anatomy of fault effects across the abstraction layers and identify the sources of error in well-established transient fault vulnerability evaluation methodologies. By providing insights for all distinct system layers, we showcase that the evaluation should take into consideration all faults that arrive from the underlying hardware as well as their distribution. We additionally quantify the level of error in a PVF estimation that can be attributed to the microarchitecture and the architecture. Current established methodologies fail to capture these aspects and can potentially lead to misleading findings. We experimentally show how PVF estimation can follow opposite (and thus misleading) trends compared to the correct, full-stack Architectural Vulnerability Factor (AVF) estimation and explain the reasons why the higher-level methodologies provide diverging results by showing the anatomy of faults manifestation across the layers. Our experiments are performed on an Armv8 microprocessor model, using different input datasets to thoroughly demonstrate our insights.

Classroom experiments on technology licensing: Royalty stacking, cross-licensing, and patent pools

The authors present two classroom experiments on technology licensing. The first classroom experiment introduces the concept of royalty stacking. Students learn that noncooperative pricing of royalties for complementary intellectual property rights leads to a double-marginalization effect. Cooperation solves the problem and is welfare-improving. The second classroom experiment introduces students to cross-licensing. It shows that reciprocal royalty payments dampen competition. The classroom experiments stimulate discussions of technology licensing, intellectual property rights, different royalty structures, patent pools, and technology standards. The authors present the experimental procedures and suggest routes for the discussion.

A high‐efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression

SummarySophisticated systems take advantage of approximate circuits for energy management. A gate‐level structure is introduced to make a novel imprecise full adder (FA) cell by the gate diffusion input (GDI) strategy. The carbon nanotube field‐effect transistor (CNTFET) technology lowers the FA power, and the swing issue is resolved by the dynamic threshold (DT) technique. The FA specifications are 10 transistors, two internal nodes, 0.191‐μm2 area, three errors, and an error rate (ER) of 37.5%. Some inputs are directly passed to the final stage of the FA to reduce the delay and dynamic power. The FA is used in three 4:2 compressors with 12, 16, and 20 transistors, respectively. The compressors are based on the modified stacking concept to attain low power, small area, and high speed. The compressors are used up in the partial product reduction tree (PPRT) of a new 8‐bit inexact multiplier. Regarding the multiplier, the power–delay product (PDP) is decreased by 25.21%, and the normalized mean error distance (NMED) shows high accuracy. An imprecise discrete cosine transform (DCT) is implemented by the multiplier for image compression, and compared with the literature, the peak signal‐to‐noise ratio (PSNR) and structural similarity index metric (SSIM) are amended by 8.26% and 7.29%, respectively.

Toward a Stackable CO2-to-CO Electrolyzer Cell Design─Impact of Media Flow Optimization

Aqueous CO2-to-CO electrolysis is a promising technology for closing the carbon cycle and defossilizing industrial processes. Considering the technological readiness, consensus has been achieved about using silver as a stable and selective electrocatalyst for the CO2-to-CO reduction reaction in aqueous electrolyte. On the other hand, challenges such as media flow management, component stability, and force distribution are still associated with improving the process performance and developing a stackable cell concept to meet industrially relevant levels. We therefore report on a promising stack concept with continuous flowcells operated with gas diffusion electrodes (GDEs). To enhance the CO2-to-CO conversion efficiency, dedicated media flow chambers were developed on two levels. In the gas chamber, which touches the GDE from the far side of the anode, the feed gas flow and distribution over the GDE were controlled by introducing various gas path architectures in a modular flowcell. In addition, an ionically conductive spacer was implemented in the catholyte chamber, which is adjacent to the opposite side of the GDE. The effect of these modifications on the cell voltage, selectivity, and overall conversion was investigated at 100 mA/cm2 with varying CO2 feed gas flow and concentration. Noteworthy, an optimized feed gas distribution generated an increase of the Faraday efficiency for CO under reduced CO2 supply. Furthermore, the implementation of the spacer enhanced the process stability by suppressing gas-bubble-induced noise in the cell voltage measurements. By functioning as support structures to the GDE, the combined modifications provided the cell with mechanical integrity and allowed an ionic and electric contact over the full active cell area, which is required for both stacking and upscaling of the cell. The corresponding performance was demonstrated by a two-cell short-stack.

Impacts of access to and use of electricity on households’ economic status in selected informal settlement areas of <i>Woreda 12</i>, Yeka Sub City, Addis Ababa, Ethiopia

At present, although electricity is essential for all human beings, it is not equally accessible to all. This paper analyzed the impact of access to and use of electricity on the economic status of informal settlements in Addis Ababa based on 450 households drawn from three sites of Woreda 12, Yeka Sub-City. The respondents were selected using proportional random sampling method and data were analyzed using descriptive statistics and Endogenous Switching Regression (ESR) models. The study revealed that non-users of electricity shifted more family labor to domestic activities, baked Injera less frequently per week, owned small number of home-based businesses, and used less alternative fuels than electricusers. However, due to lack of reliable energy supply and food consumption behaviors (FCBs), households do not completely rely on a single energy source. These situations could draw the attention of the government to provide reliable electric supply to non-users of electricity living sporadically mixed with electric-users, close to electric facilities and change households’ energy consumption behaviors using alternative energy sources with the concept of energy stacking.

Path Generation Protocol to Improve Lifetime of WSN

In WSN sensor nodes are connected to their neighbor nodes by a wireless channel and these all nodes are operated on a battery to perform any operations. So improving the lifetime of WSN is a major research challenge by effective utilization of each and every node's energy. The lifetime of WSNs can be improved in three steps: path creation, path selection, and power saving. In existing works, path selection has the major role to utilize and enhance lifetime. In the proposed PStack algorithm, path generation is a major concern, and routing is applied. It takes advantage of and solves the limitations of existing algorithms using the stack concept in WSN. The proposed algorithm shows a better result than the improved LEACH protocol because it uses the data structure with graph theory.

Fences or stacks: theoretical considerations regarding references in patents

Patent citations are an important indicator for studying science and technology interaction. Yet, empirical and conceptual studies of referencing practices in patents are largely lacking, which has resulted in an under-theorised understanding of patent citations. This study analyses previous research on patent citations and discusses these in relation to citation theories developed within science studies and bibliometrics. The ambition is, however, to advance beyond a comparative approach by adding an additional layer of analysis in which the overarching rhetorical function of references in patents and papers is considered. The analysis shows how referencing in patents have distinguishing characteristics in terms of who cites, the temporality of referencing, national and international context, quantity of references, and incentives for citing. These characteristics are discussed using the concept of fencing and stacking. Fencing illustrates how references in patents are used to demarcate claims, while the stacking of references in scientific papers is an act of cumulative persuasion. Substantial rhetorical and epistemological differences exist in how references are used in patents and papers, and these differences have implications for how citations patterns can be interpreted. The conceptualisation of referencing as fencing and stacking is suggested as a possible framework for interpreting empirical studies of patent citations. Overall, it is argued that a further theoretical, and empirical, understanding of referencing practices in patents are need in order to contextualise and problematise patent citations, and their current use in research and policy.

High precision brain tumor classification model based on deep transfer learning and stacking concepts

In this article, we proposed an intelligent clinical decision support system for the detection and classification of brain tumor from risk of malignancy index (RMI) images. To overcome the lack of labeled training data needed to train convolutional neural networks, we have used a deep transfer learning and stacking concepts. For this, we choosed seven convolutional neural networks (CNN) architectures already pre-trained on an ImageNet dataset that we precisely fit on magnetic resonance imaging (MRI) of brain tumors collected from the brain tumor segmentation (BraTS) 19 database. To improve the accuracy of our global model, we only predict as output the prediction that obtained the maximum score among the predictions of the seven pre-trained CNNs. We used a 10-way cross-validation approach to assess the performance of our main 2-class model: low-grade glioma (LGG) and high-grade glioma (HGG) brain tumors. A comparison of the results of our proposed model with those published in the literature, shows that our proposed model is more efficient than those published with an average test precision of 98.67%, an average f1 score of 98.62%, a test precision average of 98.06% and an average test sensitivity of 98.33%.

(Invited) Some Recent Progress in Ferroelectric Memory Technology

Ferroelectric memory, based on the persistent remnant polarization of certain ferroelectric materials that are switchable by an appropriate applied field, has rekindled tremendous interest ever since the discovery of HfO2-base ferroelectrics [1], and both the 1T1C based ferroelectric random-access memory (FeRAM) and the 1T based ferroelectric-gated field-effect-transistor (FeFET) variety have made significant progress. In this paper, we will review some of the important progress that we have made in both areas, while standing on the shoulders of other previous contributors, starting with the FeRAM technology below.The cell structure of FeRAM is similar to that of a DRAM structure, except that the storage capacitor is replaced by a ferroelectric one, leading to the possibility of nonvolatility without the need for a power-hungry refresh operation of the DRAM. Because of challenges concerning CMOS compatibility, physical thickness scalability, and inability to build 3D ferroelectric capacitors, the traditional perovskite-based ferroelectric materials have prevented the FeRAM cell size from further scaling down beyond the 130-nm technology node, which has confined the current FeRAM products to very limited niche markets [1]. The introduction of HfO2 based ferroelectrics has turned out to be a game changer, as high- quality and scalable ferroelectric capacitors have since been reported [1]. Among various doped and even undoped HfO2 ferroelectric thin films, the HfxZr1-xO2 (HZO) system has attracted extra attention because of its wide composition range and relatively low processing temperature for the formation of the ferroelectric phase (o-phase), making it potentially compatible with Back-End-of-Line (BEOL) process [1]. Here we will present the results of our study on a leading foundry’s BEOL-processed HZO-based ferroelectric capacitors over a wide range of areas (10-2 to 103 µm2) on 12-in wafers [2]. Some critical issues, including wake-up behavior, endurance, retention, size dependence, temperature dependence, and uniformity across the wafers will all be presented and discussed, along with their potential for automotive applications at elevated temperatures. Furthermore, we proposed and demonstrated a novel 6T/4C dual-storage-port NVSRAM by integrating two pairs of HZO-based ferroelectric capacitors onto SRAM cells through the BEOL process, which is promising for numerous IoT applications [3].More coverage of this talk will focus on FeFET cells made by the same foundry using their conventional front-end CMOS process, except for the ferroelectric gate stack of the MOS transistor. It should be noted that the FeFET cell structure was proposed decades ago but failed to commercialize, primarily because of the retention problem associated with the traditional perovskite-based ferroelectric materials [4,5]. The relatively short retention time of those perovskite-based ferroelectric FeFETs , although cannot meet the requirements of nonvolatile memory technology, is more than adequate for DRAM applications. And a 1-T ferroelectric DRAM technology based on FeFETs, named FEDRAM, was proposed [6,7]. One major attraction of the HfO2-based FeFET is its significantly longer retention. In this talk, we will discuss the underlying mechanisms contributing to the retention loss, including the presence of the depolarization field and gate leakage followed by trapping [4]. Moreover, we will present the reason why the FeFET cell based on the ferroelectric HfO2 can achieve better retention time compared with those based on PZT and SBT [8]. While the HfO2-based FeFETs have demonstrated impressive memory retention, they are suffering from limited endurance. We will discuss the causes of such reliability concerns [9]. It will be shown that the endurance failure is mainly attributed to the charge trapping and trap generation in the gate stack, rather than fatigue of polarization in the HfO2 ferroelectric layer. The understanding of the mechanisms behind the retention loss and the endurance issues will help us to formulate possible strategies for further advancing the pathway toward commercialization of the FeFET memory technology. The nearly identical memory cell structure as well as the similar program/erase algorithm between FeFET and NAND Flash memory naturally leads to the concept of 3D ferroelectric memory stacks based on FeFET cells, as proposed by the Yale group [10]. This patented 3D memory technology will also be briefly discussed.[1] T. Mikolajick et al.,MRS Bulletin 43 340(2018) [2] H. Jiang et al., IMW2020 [3] H. Jiang et al., JEDS 8 935(2020) [4] T. P .Ma et al., IEEE EDL 23 386(2002) [5] X. Pan et al., Appl. Phys. Lett. 99 01305 (2011) [6] J.-P. Han et al., Integr. Ferroelect. 27 1053 (1999) [7] K.-H. Kim et al., IEEE EDL 23 82 (2002) [8] N. Gong et al., IEEE EDL 37 (9) 1123 (2016) [9] N. Gong et al., IEEE EDL 39 (1) 15 (2017). [10] Xiao Sun et al., U.S. Patent No. 9,818,848(2017)

DFMA analysis of front axle assembly of an excavator

The front axle assembly of a hydraulic excavator consists of front axle, stub axle and thrust bearing. The front axle carries the weight of the front part of the vehicle, as well as to facilitate steering and to absorb shocks due to road surface conditions. In addition, it absorbs torque applied on it due to the braking of vehicle. It is constructed with I-section in center and the ends are made either circular or elliptical. Stub axles are connected to the front axle by king pins. Front wheels are mounted on stub axle’s arrangement for steering. A nominal assembly gap in the front axle assembly has to be maintained for better performance and for easy maneuvering of the vehicle during operation. The gap depends on the model and the assembly dimensions of the front axle, stub axle and thrust bearing. A typical value ranging from 0.1 and 0.5mm is required for one particular model being manufactured by the local industry. It is reported that there are more number of assembly rejections in maintaining the said gap which lead to higher cost and downtime due to rework or interchange of parts. To reduce this, DFMA analysis was carried out using the concept of stack up tolerance to reduce the rejections and improve the performance of front axle assembly, without affecting the manufacturing.

Classroom Experiments on Technology Licensing: Royalty Stacking, Cross-Licensing and Patent Pools

We present two classroom experiments on technology licensing. The first classroom experiment introduces the concept of royalty stacking. The students learn that non-cooperative pricing of royalties for complementary intellectual property rights leads to a double-marginalization effect. Cooperation solves the problem and is welfare improving. The second classroom experiment introduces students to cross-licensing. It shows that reciprocal royalty payments dampen competition. The classroom experiments stimulate discussions of technology licensing, intellectual property rights, different royalty structures, patent pools and technology standards. We present the experimental procedures, and suggests routes for the discussion.

An Accurate Model for Threshold Voltage Analysis of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor

In this article, an accurate representation of threshold voltage for double metal double gate (DMDG) device structure has been initiated. It is the lowest gate-source electromotive force at which the device can kick off to conduct. This paper also deliberates a comparison between the high-k medium and SiO2 as an oxide substance along with that considers the gate stack concept. Use of a promising high-k substance HfO2, reduces the small channel effect which is generated due to downsizing the device. The main challenge is to overcome the short channel effect that is generated due to scaling down the device. The model has been established by varying several criteria like channel length, film thickness, oxide thickness, temperature change, work function difference and drain source voltage. So that a clear reflection can be seen how the threshold voltage changes with several parameters. For all the cases, the implementations with high-k material show better execution in case of reducing short channel effects (SCEs) that are mainly generated due to reducing the device structure. In this article, the drain induced barrier lowering (DIBL) and subthreshold swing (SS) have also been modelled for the device structure. Extreme conformity can be noticed between the analytical model and TCAD result.

Simplified anode architecture for PEMFC systems based on alternative fuel feeding: Experimental characterization and optimization for automotive applications

The need to reduce PEMFC systems cost as well as to increase their durability is crucial for their integration in various applications and especially for transport applications. A new simplified architecture of the anode circuit called Alternating Fuel Feeding (AFF) offers to reduce the development costs. Requiring a new stack concept, it combines the simplicity of Dead-End Anode (DEA) with the operation advantages of the hydrogen recirculation. The three architectures (DEA, recirculation and AFF) are compared in terms of performance on a 5-kW test bench in automotive conditions, through a sensitivity analysis. A gain of 17% on the system efficiency is observed when switching from DEA to AFF. Moreover, similar performances are obtained both for AFF and for recirculation after an accurate optimization of the AFF tuning parameters. Based on DoE data, a gain of 25% on the weight of the anodic line has been identified compared to pulsed ejector architecture and 43% with the classic recirculation architecture with blower only (Miraï).

(Invited) Some Recent Progress in Ferroelectric Memory Technology

Ferroelectric memory, based on the persistent remnant polarization of certain ferroelectric materials that are switchable by an appropriate applied field, has rekindled tremendous interest ever since the discovery of HfO2-base ferroelectrics [1], and both the one-transistor-one-capacitor (1T1C) based ferroelectric random-access memory (FeRAM) and the single-transistor (1T) based ferroelectric-gated field-effect-transistor (FeFET) variety have made significant progress. In this paper, we will review some of the important progress that we have made in both areas, while standing on the shoulders of other previous contributors, starting with the FeRAM technology below.The cell structure of FeRAM is similar to that of a DRAM structure, except that the storage capacitor is replaced by a ferroelectric one, leading to the possibility of nonvolatility without the need for a power-hungry refresh operation of the DRAM. Because of challenges concerning CMOS compatibility, physical thickness scalability, and inability to build 3D ferroelectric capacitors, the traditional perovskite-based ferroelectric materials (such as PZT and SBT) have prevented the FeRAM cell size from further scaling down beyond the 130-nm technology node, which has confined the current FeRAM products to very limited niche markets [1]. The introduction of hafnium oxide (HfO2)-based ferroelectrics has turned out to be a game changer, as high-quality and scalable ferroelectric capacitors have since been reported, including TiN/Al:HfO2/TiN-based 3D deep-trench capacitors [1]. Among various doped and even undoped HfO2 ferroelectric thin films, the HfxZr1-xO2 system has attracted extra attention because of its wide composition range and relatively low processing temperature (<= 400 0C), making it potentially compatible with Back-End-of-Line (BEOL) process [1]. Here we will present the results of our study on a leading foundry’s BEOL-processed Hf0.5Zr0.5O2-based ferroelectric capacitors over a wide range of areas (10-2 to 103 µm2) on 12-in wafers. Some critical issues, including wake-up behavior, endurance, retention, size dependence, temperature dependence, and uniformity across the wafers have all been systematically characterized and will be discussed, as well as their potential for automotive applications at elevated temperatures.More coverage of this talk will be focused on FeFET cells made by the same foundry using their conventional front-end CMOS process except for the ferroelectric gate stack of the MOS transistor. It should be noted that the FeFET cell structure was proposed decades ago but failed to commercialize primarily because of the retention problem associated with the traditional perovskite-based ferroelectric materials [2,3]. The relatively short retention time of those perovskite-based ferroelectric FeFETs , although cannot meet the requirements of nonvolatile memory technology, is more than adequate for DRAM applications. And a 1-T ferroelectric DRAM technology based on FeFETs, named FEDRAM, was proposed [4,5]. One major attraction of the HfO2-based FeFET is its significantly longer retention. In this talk, we will discuss the underlying mechanisms contributing to the retention loss, including the presence of the depolarization field and gate leakage followed by trapping [2]. Moreover, we will present the reason why the FeFET cell based on the ferroelectric HfO2 can achieve better retention time compared with those based on PZT and SBT [6]. While the HfO2-based FeFETs have demonstrated impressive memory retention, they are suffering from limited endurance. We will discuss the causes of such reliability concerns [7]. It will be shown that the endurance failure is mainly attributed to the charge trapping and trap generation in the gate stack, rather than fatigue of polarization in the HfO2 ferroelectric layer. The understanding of the mechanisms behind the retention loss and the endurance issues will help us to formulate possible strategies for further advancing the pathway toward commercialization of the FeFET memory technology.The nearly identical memory cell structure as well as the similar program/erase algorithm between FeFET and NAND-Flash memory naturally leads to the concept of 3D ferroelectric memory stacks based on FeFET cells, as proposed by the Yale group [8]. This patented 3D memory technology will also be briefly discussed.This work was supported by the National Science Foundation (NSF) under Award No: 1609162.

Enhancing the operational flexibility of thermal power plants by coupling high-temperature power-to-gas

The increasing penetration of intermittent renewable power challenges the stability of the electrical grid, thus coal power plants are usually required to extend the operation range by reducing the minimum load. This work proposes a concept of coupling solid-oxide cell stack based power-to-gas with coal power plants to allow for dual functions of (1) storing excess renewable electricity and (2) reducing the minimum load of coal power plants by combustion stabilization with oxygen-rich air from power-to-gas. The performance and operating strategy of such an integrated plant are evaluated with detailed off-design characteristics of the considered coal power plants. The results show that the integration of power-to-gas affects the distribution of the heat absorbed by radiative and convective heat exchangers in the boiler, stabilizes coal combustion, and reduces the superheat degree of live/reheated steam. It allows the power plant for operating at a significantly low load of down to 22% of the nominal load, compared with 40% before the coupling; meanwhile, a very limited penalty is caused with the plant efficiency reduced from 34.4% down to 34.1% (with 13% of the normalized power-to-gas capacity). Minimizing the power-to-gas contribution to the accommodated renewable power is advantageous for a minimal CO2 emission; nevertheless, maximizing the power-to-gas contribution with the coal power plant at high load allows for a maximal system efficiency.

A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter/Mixer

A low-power interferer-robust mixer-first receiver front end that uses a novel capacitive stacking technique in a bottom-plate N-path filter/mixer is proposed. Capacitive stacking is achieved by reading out the voltage from the bottom plate of N-path capacitors instead of their top plate, which provides a $2\times $ voltage gain after downconversion. A step-up transformer is used to improve the out-of-band (OOB) linearity performance of small switches in the N-path mixer, thereby reducing the power consumption of switch drivers. This article explains the concept of implicit capacitive stacking and analyzes its transfer characteristics. A prototype chip, fabricated in 22-nm fully depleted silicon on insulator (FDSOI) technology, achieves a voltage gain of 13 dB and OOB IIP3/IIP2 of +25/+66 dBm with 5-dB noise figure while consuming only 600 $\mu \text{W}$ of power at $f_{\mathrm{ LO}}=1$ GHz. Thanks to the transformer, the prototype can operate in the input frequency range of 0.6–1.2 GHz with more than 10-dB voltage gain and 5–9-dB noise figure. Thus, it opens up the possibility of low-power software-defined radios.