SRAM Physical Unclonable Function Research Articles

Reliability improvement of SRAM PUFs based on a detailed experimental study into the stochastic effects of aging

Physical Unclonable Functions (PUFs) have gained attention as a lightweight hardware security primitive. In particular, the SRAM-based PUF uses the unpredictable power-up value of the cells within an SRAM. Although these values should ideally be always the same within each SRAM to accomplish a correct PUF operation, this is often not the case, especially when factors like circuit aging are considered. While certain studies explore the effects of aging on SRAM PUFs, they often simplify the analysis. For instance, some studies assume that only Bias Temperature Instability (BTI) contributes to circuit degradation while others evaluate the overall degradation without accounting for the stochastic effects of aging on each individual cell. In this work, we first perform a detailed characterization of the nature of aging in SRAM PUFs, demonstrating that the impact of Non-Conductive Hot-Carrier Injection cannot be neglected. We also show that different cells degrade differently, highlighting the importance of accounting for the stochasticity of aging. After that, a method based on the Data Retention Voltage metric to select the cells with the most stable power-up response is introduced. Using these cells to generate the PUF identifier will result in a more stable response, and thus a better PUF performance.

Design and Analysis of Secure Quasi-Adiabatic Tristate Physical Unclonable Function

Hardware security modules have become quintessential as the digital systems continue evolving. Physical Unclonable Function (PUF) is a hardware security module that exploits the intrinsic variations in manufacturability of integrated circuits. Proposed Quasi-adiabatic Tristate PUF is a weak PUF which makes use of the inherent mismatches found in the threshold voltage values of PMOS transistors, which inadvertently is introduced due to manufacturing process variations of ICs. The proposed design demonstrates lower energy consumption than those configured using comparable quasi-adiabatic logic counterparts, under varying temperature and peak voltage conditions. The design is compared using SRAM PUF design based on adiabatic logic and it is shown that the proposed one is having better uniqueness and reliability at different environmental conditions. The proposed PUF can generate 128 CRPs which can be well suited for IoT and RFID applications that require less energy to operate.

Secret-free security: a survey and tutorial

“Classical keys,” i.e., secret keys stored permanently in digital form in nonvolatile memory, appear indispensable in modern computer security—but also constitute an obvious attack target in any hardware containing them. This contradiction has led to perpetual battle between key extractors and key protectors over the decades. It is long known that physical unclonable functions (PUFs) can at least partially overcome this issue, since they enable secure hardware without the above classical keys. Unfortunately, recent research revealed that many standard PUFs still contain other types of “secrets” deeper in their physical structure, whose disclosure to adversaries breaks security as well: Examples include the manufacturing variations in SRAM PUFs, the power-up states of SRAM PUFs, or the signal delays in Arbiter PUFs. Most of these secrets have already been extracted in viable attacks in the past, breaking PUF-security in practice. A second generation of physical security primitives now shows potential to resolve this remaining problem, however. In certain applications, so-called Complex PUFs, SIMPLs/PPUFs, and UNOs are able to realize not just hardware that is free of classical keys in the above sense, but completely “secret-free” instead. In the resulting hardware systems, adversaries could hypothetically be allowed to inspect every bit and every atom, and learn any information present in any form in the system, without being able to break security. Secret-free hardware would hence promise to be innately and permanently immune against any physical or malware-based key-extraction: There simply is no security–critical information to extract anymore. Our survey and tutorial paper takes the described situation as starting point, and categorizes, formalizes, and overviews the recently evolving area of secret-free security. We propose the attempt of making hardware completely secret-free as promising endeavor in future hardware designs, at least in those application scenarios where this is logically possible. In others, we suggest that secret-free techniques could be combined with standard PUFs and classical methods to construct hybrid systems with notably reduced attack surfaces.

Reliability Improvement on SRAM Physical Unclonable Function (PUF) Using an 8T Cell in 28 nm FDSOI

An 8T cell is proposed to improve reliability and radiation tolerance of the static random-access memory (SRAM) physical unclonable function (PUF) which is formed by adding two cascode PMOS transistors biased at on-state to standard 6T cell. Two custom SRAM PUFs in the same batch consisting of 6T cells and 8T cells using 28nm FDSOI process were employed to evaluate characteristics with respect of bit error rate (BER) and inter-chip hamming distance (HD) under an increase of Co-60 total ionizing dose, various supply voltage, ramp-up time, and temperature. According to the experimental result, the BER of the proposed SRAM PUF decreased by 2X under various conditions with better radiation tolerance compared with the 6T one. Both kinds of SRAM PUF have similar inter-chip HD closed to 50%, but the proposed prototype has less variation thanks to better reliability. When supply voltage, ramp-up time, and temperature conditions were set to 400 mV, 100 ms, and 25°C respectively, the proposed SRAM PUF can achieve the lowest BER of only 0.72%. Some design tips of reliable and rad-hard SRAM PUF are given as the design guidance.

Effects of Total Ionizing Dose on SRAM Physical Unclonable Functions

The effects of total ionizing dose (TID) on static random access memory (SRAM) physical unclonable functions (PUFs) are studied through X-ray and proton irradiation of commercially available SRAM. Negative shifts in the fractional Hamming weight (FHW) were measured with increasing TID, indicating a migration of bistable cells toward logic low. Additionally, positive shifts in the intra-die fractional Hamming distance (FHD) were measured and indicate changes to the virtual fingerprint of an SRAM PUF with TID, especially in devices that were dosed while holding data. Shifts in inter-die FHD were negligible, allowing individual SRAMs still to be easily identified based on the FHD between a known and unknown sample even after moderate amounts of TID. In some cases, SRAMs could still be identified by their PUFs after the devices had failed. In all cases, the irradiated SRAM devices retained their virtual fingerprint after recovery through annealing.

Lightweight hardware fingerprinting solution using inherent memory in off-the-shelf commodity devices

An emerging technology known as Physical unclonable function (PUF) can provide a hardware root-of-trust in building the trusted computing system. PUF exploits the intrinsic process variations during the integrated circuit (IC) fabrication to generate a unique response. This unique response differs from one PUF to the other similar type of PUFs. Static random-access memory PUF (SRAM-PUF) is one of the memory-based PUFs in which the response is generated during the memory power-up process. Non-volatile memory (NVM) architecture like SRAM is available in off-the-shelf microcontroller devices. Exploiting the inherent SRAM as PUF could wide-spread the adoption of PUF. Therefore, in this study, we evaluate the suitability of inherent SRAM available in ATMega2560 microcontroller on Arduino platform as PUF that can provide a unique fingerprint. First, we analyze the start-up values (SUVs) of memory cells and select only the cells that show random values after the power-up process. Subsequently, we statistically analyze the characteristic of fifteen SRAM-PUFs which include uniqueness, reliability, and uniformity. Based on our findings, the SUVs of fifteen on-chip SRAMs achieve 42.64% uniqueness, 97.28% reliability, and 69.16% uniformity. Therefore, we concluded that the available SRAM in off-the-shelf commodity hardware has good quality to be used as PUF.

Resilient Password Manager Using Physical Unclonable Functions

The offline dictionary attacks on the database of passwords (PW) or even hashed PW are damaging as a single server break-in leads to many compromised PWs. In this regard, using Physical Unclonable Functions (PUFs) to increase the security of PW manager systems has been recently proposed. Using PUFs allows replacing the hashed PW with PUF responses, which provide an additional hardware layer of security. In this way, even with accessing the database, an adversary should have physical control of the PUF to find the PWs. However, such a scheme cannot operate without a backup in case of catastrophic failure of the PUFs. The likelihood of a failure is low unless the opponent finds a way to destroy the PUF. The scheme used in this article includes a mechanism to make the system works consistently if the PUF fails, with redundant elements. In this method, two PUF outputs are saved in the database to register a user. In authentication, the first PUF output in the database is just checked. The second PUF output in the database is only checked in the exceptional cases when the first PUF does not work correctly; therefore, both false reject rates and latencies are not degraded. A PW manager node is implemented using a low-cost microcontroller, SRAM PUF, and nonvolatile SRAM. The nonvolatile SRAM is embedded in the PWM node circuit as a local database. Statistical tests on the applied commercial SRAM in this article show better PUF quality than those used in previous research. Also, to handle the error in PUF responses, only the stable SRAM cells are used. This article presents the first prototype of a resilient PW manager node with an embedded local database to the best of our knowledge.

Rejection Sampling Schemes for Extracting Uniform Distribution from Biased PUFs

This paper presents an efficient fuzzy extractor (FE) construction for secure cryptographic key generation from physically unclonable functions (PUFs). The proposed FE, named acceptance-or-rejection (AR)-based FE, utilizes a new debiasing scheme to extract a uniform distribution from a biased PUF response. The proposed debiasing scheme employs the principle of rejection sampling, and can extract a longer debiased bit string compared to those of conventional debiasing schemes. In addition, the proposed AR-based FE is extended to ternary PUF responses (i.e., ternary encoding of a PUF response). These responses can be derived according to cell-wise reliability of the PUF and are promising for extraction of stable and high-entropy responses from common PUFs. The performance of the AR-based Fes is evaluated through an experimental simulation of PUF-based key generation and compared with conventional FEs. We confirm that the proposed AR-based FE can achieve the highest efficiency in terms of PUF and nonvolatile memory (NVM) sizes for various PUF conditions among the conventional counterparts. More precisely, the AR-based FE can realize a 128-bit key generation with up-to 55% smaller PUF size or up-to 72% smaller NVM size than other conventional FEs. In addition, the ternary AR-based FE is up to 55% more efficient than the binary version, and can also achieve up-to 63% higher efficiency than conventional counterparts. Furthermore, we show that the AR-based FE can be applied to PUFs with local biases (e.g., biases depending on cell location in SRAM PUFs), unlike all the conventional schemes, for which only global (or identical) biases are assumed.

Design and implementation of robust and low-cost SRAM PUF using PMOS and linear shift register extractor

The robustness of Static random access memory (SRAM) Physical unclonable functions (PUFs) is threatened by the state change of the power-up value (R) at different temperatures. The voltage ramp-up time Tramp is one of the factors that can affect the stability of R. Some studies have been performed on the Tramp of commercial SRAM chips at the microsecond (μs) level. In this paper, a robust and low cost SRAM PUF using a p-channel metal oxide semiconductor (PMOS) as a power switch to enhance the stability of R is proposed. Tramp is as fast as 11 V/ns. The proposed SRAM PUF has a linear shift register extractor, with an extraction rate as high as 7/18 and no helper data in contrast to traditional von Neumann extractor. This chip has been fabricated using 0.11 μm ultra-low-leakage technology. The experiment results show that R becomes stable at [-40 °C, 85 °C], and a simple lightweight error correcting codes (ECC) can be used in SRAM PUF.

Lightweight (Reverse) Fuzzy Extractor With Multiple Reference PUF Responses

A physical unclonable function (PUF), like a fingerprint, exploits manufacturing randomness to endow each physical item with a unique identifier. One primary PUF application is the secure derivation of volatile cryptographic keys using a fuzzy extractor (FE) comprising: 1) a secure sketch and 2) an entropy extractor. Although the entropy extractor can be lightweight, the overhead of the secure sketch responsible for correcting naturally noisy PUF responses is usually high. We observe that, in general, response unreliability with respect to an enrolled reference measurement increases with increasing differences between the in-the-field PUF operating condition and the operating condition used in evaluating the enrolled reference response. For the first time, we exploit such an inadvertent but important observation. In contrast to the conventional single reference response enrollment, we propose enrolling multiple reference responses (MRRs) subject to the same challenge but under multiple distinct operating conditions. The critical observation here is that one of the reference operating conditions is likely to be closer to the operating condition of the field deployed PUF, thus resulting in minimizing the expected unreliability when compared to the single reference under the nominal condition. As a consequence, MRR greatly reduces the demand for the expected number of erroneous bits requiring correction and, subsequently, achieves a significant reduction in the error correction overhead. The significant implementation efficiency gains from the proposed MRR method are demonstrated from software implementations of FEs on batteryless resource constraint computational radio frequency identification devices, where realistic PUF data are collected from intrinsic static random access memory PUFs.

A reliable PUF in a dual function SRAM

The Internet of Things (IoTs) employs resource-constrained sensor nodes for sensing and processing data that require robust, lightweight cryptographic primitives. The SRAM Physical Unclonable Function (SRAM-PUF) is a potential candidate for secure key generation. An SRAM-PUF is able to generate random and unique cryptographic keys based on start-up values by exploiting intrinsic manufacturing process variations. The reuse of the available on-chip SRAM memory in a system as a PUF might achieve useful cost efficiency. However, as CMOS technology scales down, aging-induced Negative Bias Temperature Instability (NBTI) becomes more pronounced resulting in asymmetric degradation of memory bit cells after prolonged storage of the same bit values. This causes unreliable start-up values for an SRAM-PUF. In this paper, the on-chip memory in the ARM architecture has been used as a case study to investigate reliability in an SRAM-PUF. We show that the bit probability in a 32-bit ARM instruction cache has a predictable pattern and hence predictable aging. Therefore, we propose using an instruction cache as a PUF to save silicon area. Furthermore, we propose a bit selection technique to mitigate the NBTI effect. We show that this technique can reduce the predicted bit error in an SRAM-PUF from 14.18% to 5.58% over 5 years. Consequently, as the bit error reduces, the area overhead of the error-correction circuitry is about 6 × smaller compared to that without a bit selection technique.

Improving uniformity and reliability of SRAM PUFs utilizing device aging phenomenon for unique identifier generation

SRAM Physical Unclonable Functions (PUFs) utilize start-up values generated by random variations in the fabrication process. However, the random variations can generate biased power-up data, which can degrade the uniformity below the target. In addition, very small mismatches can prevent power-up data from being repeated, deteriorating the reliability. This paper presents a post-fabrication technique that can improve the uniformity and the reliability of SRAM PUFs by utilizing device aging phenomenon through two functional steps. In the first step, the proposed technique controls the polarity of the device aging in each SRAM cell using the power-up value for uniformity improvement. Once a target uniformity is achieved from an SRAM array, we inject device aging into each SRAM cell in a way of increasing the mismatches between two cross-coupled inverters. An SRAM PUF test chip fabricated in 65 nm CMOS technology validated the effectiveness of device aging in enhancing the uniformity and the reliability of the SRAM PUF.

A secure arbiter physical unclonable functions (PUFs) for device authentication and identification

Recent fourth industrial revolution, industry4.0 results in lot of automation of industrial processes and brings intelligence in many home appliances in the form of IoT, enhances M2M / D2D communication where electronic devices play a prominent role. It is very much necessary to ensure security of those devices. To provide reliable authentication and identification of each device and to abort the counterfeiting from the unauthorized foundries Physical Unclonable Functions (PUFs) emerged as a one of the promising cryptographic hardware security solution. PUF is function, mathematically modeled by using uncontrollable/ unavoidable random variances of the fabrication process of the ICs. These variances can generate unpredictable, random responses can be used to overcome the difficulties such as storing the keys in non-volatile memories (NVMs) in the classical cryptography. A wide variety of PUF architectures such as Arbiter PUFs, Ring oscillator PUFs, SRAM PUFs proposed by authors. But due to its design complexity and low cost, Delay based Arbiter PUFs (D-PUFs) are considering to be a one of the security primitives in authentication applications such as low-cost IoT devices for secure key generation. This paper presents a review on the different types of Delay based PUF architectures proposed by the various authors, sources to exhibit the physical disorders in ICs, methods to estimate the Performance metrics and applications of PUF in different domains.

A secure arbiter physical unclonable functions (PUFs) for device authentication and identification

Recent fourth industrial revolution, industry4.0 results in lot of automation of industrial processes and brings intelligence in many home appliances in the form of IoT, enhances M2M / D2D communication where electronic devices play a prominent role. It is very much necessary to ensure security of those devices. To provide reliable authentication and identification of each device and to abort the counterfeiting from the unauthorized foundries Physical Unclonable Functions (PUFs) emerged as a one of the promising cryptographic hardware security solution. PUF is function, mathematically modeled by using uncontrollable/ unavoidable random variances of the fabrication process of the ICs. These variances can generate unpredictable, random responses can be used to overcome the difficulties such as storing the keys in non-volatile memories (NVMs) in the classical cryptography. A wide variety of PUF architectures such as Arbiter PUFs, Ring oscillator PUFs, SRAM PUFs proposed by authors. But due to its design complexity and low cost, Delay based Arbiter PUFs (D-PUFs) are considering to be a one of the security primitives in authentication applications such as low-cost IoT devices for secure key generation. This paper presents a review on the different types of Delay based PUF architectures proposed by the various authors, sources to exhibit the physical disorders in ICs, methods to estimate the Performance metrics and applications of PUF in different domains.

Controlling the Reliability of SRAM PUFs With Directed NBTI Aging and Recovery

As the Internet of Things continues to spread, devices within it are given more personal information which must be protected. To provide this protection, a device known as a physical unclonable function (PUF) has been devised which takes advantage of natural variations in silicon to create a unique fingerprint which can be used for secret key generation and authentication. This fingerprint is often based upon settlement of a race condition in competing circuits which is decided by process variations and noise. In this paper, we focus on the SRAM PUF, whose fingerprint is determined by the tendency of each cell to contain a 0 or 1 after it powers on. These cells are susceptible to negative-bias temperature instability (NBTI) while storing data, which pushes their power-on tendencies away from the data they contain. We present a method by which the success rate of an SRAM to produce a correct fingerprint can be reduced to 0% in only one day using NBTI activated and accelerated by elevated voltage and temperature, followed by another method in which it can be restored to nearly 100% in less than two days using active, accelerated NBTI recovery with negative voltage and elevated temperature.

Pitfall of the Strongest Cells in Static Random Access Memory Physical Unclonable Functions.

Static Random Access Memory (SRAM) Physical Unclonable Functions (PUFs) are some of the most popular PUFs that provide a highly-secured solution for secret key storage. Given that PUF responses are noisy, the key reconstruction must use error correcting code (ECC) to reduce the noise. Repetition code is widely used in resource constrained systems as it is concise and lightweight, however, research has shown that repetition codes can lead to information leakage. In this paper we found that the strongest cell distribution in a SRAM array may leak information of the responses of SRAM PUF when the repetition code is directly applied. Experimentally, on an ASIC platform with the HHGRACE 0.13 μm process, we recovered 8.3% of the measured response using the strongest cells revealed by the helper data, and we finally obtained a clone response 79% similar to weak response using the public helper data. We therefore propose Error Resistant Fuzzy Extractor (ERFE), a 4-bit error tolerant fuzzy extractor, that extracts the value of the sum of the responses as a unique key and reduces the failure rate to 1.8 × 10−8 with 256 bit entropy.

A Method to Improve Reliability in a 65-nm SRAM PUF Array

A modified weak SRAM physical unclonable function (PUF) is proposed which is much more reliable than prior-art SRAM PUFs. The proposed PUF was fabricated in TSMC 65-nm process. A novel preselection test was run on these PUF arrays and is shown to eliminate all of the unstable cells (20%–25%). This PUF can drastically reduce the need for error correction codes. In addition, the preselection test can be accomplished in one VDD/temperature corner, which reduces the testing cost of finding unstable bits across many such corners, as is done in the prior art.

FPGA implementation of SRAM PUFs based cryptographically secure pseudo-random number generator

The security of cryptographic protocols depends on the security of key sequences consisting of random numbers. In this paper, we design a Cryptographically Secure Pseudo-Random Number Generator (CSPRNG), which consists of a hash based Deterministic Random Bit Generator (DRBG) and a Get Entropy module. SRAM Physical Unclonable Functions (PUFs) are regarded as entropy sources, providing entropy data with enough entropy for CSPRNG. The construction of Get Entropy module is proposed to verify the availability of SRAM PUFs and compress the entropy data into truly random seeds that are fed into DRBG. This CSPRNG can reseed itself dynamically and can monitor the entropy of entropy sources in real time. The system is implemented and tested on Altera DE2. The test results show that, the pseudo-random numbers generated by this system can pass all random tests of National Institute of Standards and Technology (NIST) SP800-22 Test Suite and the throughput is up to 598.1 Mbps. Through the security discussion, this CSPRNG is theoretically confirmed that it can be securely applied to cryptographic protocols.

Measurement of Static Random Access Memory Power-Up State Using an Addressable Cell Array Test Structure

The data stored in a static random access memory (SRAM) immediately after power-up is of practical interest for some applications, such as SRAM physical unclonable functions. In this paper, measurements of SRAM cell power-up state (i.e., whether the cell is storing 0 or 1 after the power supply is turned on) using an addressable cell array test structure are reported. The test structure provides direct access to individual transistor characteristics of many SRAM cells, which would facilitate the characterization of SRAM power-up behavior. Methods and considerations necessary for reliable and stable power-up state characterization using the test structure will be discussed and demonstrated.

Systematic Correlation and Cell Neighborhood Analysis of SRAM PUF for Robust and Unique Key Generation

A physical unclonable function (PUF) is a structure that produces a unique response, with an issued challenge (input), which can be used as an identifier or a cryptographic key. SRAM PUFs create unique responses upon power up as certain SRAM cells output a “1” or “0” with high probability due to uncontrollable process variations. A current challenge in SRAM PUFs is their sensitivity to temperature and voltage variations as well as aging. It is always challenging to make SRAM PUFs reliable and unique with algorithms that isolate stable and uncorrelated bits quickly with minimal testing (enrollment). In this paper, we explore the selection of stable and uncorrelated bits through enrollment under different conditions (temperature and voltage) and also by exploiting previously undiscovered interactions between neighboring SRAM cells. We propose neighbor influenced cell selection algorithm (NICSA) with the help of metrics that analyze the impact of each neighboring cell and each enrollment condition. The proposed NICSA helps to identify the “best” cells and conditions for stable bit selection. Besides reliability, SRAM PUF can be less unique due to systematic correlation among chips. We study the systematic correlation between SRAMs power-up values to find the uncorrelated cells among chips for better uniqueness. We have analyzed data from 5 ISSI, 3 IDT, and 3 Cypress SRAMs and our metrics identify the best neighborhood size (16 stable neighbors) and best enrollment condition pair high temperature, high voltage, and low temperature for NICSA.