A secure arbiter physical unclonable functions (PUFs) for device authentication and identification

Anil Kumar Kurra,Usha Rani Nelakuditi

doi:10.11591/ijeei.v7i1.614

Abstract

Recent fourth industrial revolution, industry4.0 results in lot of automation of industrial processes and brings intelligence in many home appliances in the form of IoT, enhances M2M / D2D communication where electronic devices play a prominent role. It is very much necessary to ensure security of those devices. To provide reliable authentication and identification of each device and to abort the counterfeiting from the unauthorized foundries Physical Unclonable Functions (PUFs) emerged as a one of the promising cryptographic hardware security solution. PUF is function, mathematically modeled by using uncontrollable/ unavoidable random variances of the fabrication process of the ICs. These variances can generate unpredictable, random responses can be used to overcome the difficulties such as storing the keys in non-volatile memories (NVMs) in the classical cryptography. A wide variety of PUF architectures such as Arbiter PUFs, Ring oscillator PUFs, SRAM PUFs proposed by authors. But due to its design complexity and low cost, Delay based Arbiter PUFs (D-PUFs) are considering to be a one of the security primitives in authentication applications such as low-cost IoT devices for secure key generation. This paper presents a review on the different types of Delay based PUF architectures proposed by the various authors, sources to exhibit the physical disorders in ICs, methods to estimate the Performance metrics and applications of PUF in different domains.

Highlights

Advances in technology from IT to IoT enhance the usage of electronic devices
HDintra is a metric that measures the response of a Physical Unclonable Functions (PUFs) under the same challenge at different fluctuating environmental conditions and supply voltage variations
Uniqueness should be 36.7% and its reliability is (82%) at 75 ̊c respectively and resist the attack such as support vector machine (SVM).To combat the attacks over PUFs to enhance authenticity Takanori Machida, Dai Yamamoto [23] proposed a Multi input-Multi output (8 by 8) PUF design in 90 nm CMOS technology by applying Monte-Carlo analysis to estimate the statistical metrics of the switching element and improved the arbiter accuracy

Summary

INTRODUCTION

Advances in technology from IT to IoT enhance the usage of electronic devices. electronic hardware security emerged as one of the serious challenge due to the penetration of electronic devices in to all spheres of people life. HDintra is a metric that measures the response of a PUF under the same challenge at different fluctuating environmental conditions and supply voltage variations. It could be done in two phases: Enrolment phase and Regeneration phase. Its consistency can be assessed by calculating the typical Inter chip Hamming Distance (HDintra) of n bit PUF responses. These m responses Rj are collected under m distinct environmental conditions. The modified PUF should distinctly different in terms of architecture and behavior

DELAY BASED ARBITER BASED PU

Sensitivity decreases

Findings

CONCLUSION