SRAM Cell Array Research Articles

Addressing Power Efficiency and Stability in SRAM: A 4x4 Cell Array Design with Enhanced Power Gating

In order to lower power consumption and leakage currents during active operation, the suggested SRAM architecture with power gating design trims the source voltage across the SRAM cell, ranging from 50 to 150 mV. Power gating based on sectors is utilized, using a self-biasing approach where the gate terminal and source of a PMOS transistor act as a diode, controlling the virtual ground. However, three challenges arise with this method in nanometer technology: the additional self- biasing transistor (SBT) occupies 5% more space, the source voltage adjustment mechanisms are not effectively implemented, and the increase in virtual ground voltage leads to bias temperature instability. To implement this design, a 4x4 SRAM cell array is constructed, consisting of 4 rows and 4 columns of 10T SRAM cells. A decoder addresses these cells, and each row represents half a byte, with control circuitry managing input and output data. Additionally, the outputs of individual cells in each column are combined using a 4-bit OR, producing a single data output point. This architecture effectively reduces power consumption while maintaining operational efficiency, making it suitable for nanometer-scale SRAM designs.

8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing

Large-scale digital computing almost exclusively relies on the von Neumann architecture, which comprises separate units for storage and computations. The energy-expensive transfer of data from the memory units to the computing cores results in the well-known von Neumann bottleneck. Various approaches aimed toward bypassing the von Neumann bottleneck are being extensively explored in the literature. These include in-memory computing based on CMOS and beyond CMOS technologies, wherein by making modifications to the memory array, vector computations can be carried out as close to the memory units as possible. Interestingly, in-memory techniques based on CMOS technology are of special importance due to the ubiquitous presence of field-effect transistors and the resultant ease of large-scale manufacturing and commercialization. On the other hand, perhaps the most important computation required for applications such as machine learning, etc., comprises the dot-product operation. Emerging nonvolatile memristive technologies have been shown to be very efficient in computing analog dot products in an in situ fashion. The memristive analog computation of the dot product results in much faster operation as opposed to digital vector in-memory bitwise Boolean computations. However, challenges with respect to large-scale manufacturing coupled with the limited endurance of memristors have hindered rapid commercialization of memristive-based computing solutions. In this paper, we show that the standard 8 transistor (8T) digital SRAM array can be configured as an analoglike in-memory multibit dot-product engine (DPE). By applying appropriate analog voltages to the read ports of the 8T SRAM array and sensing the output current, an approximate analog–digital DPE can be implemented. We present two different configurations for enabling multibit dot-product computations in the 8T SRAM cell array, without modifying the standard bit-cell structure. We also demonstrate the robustness of the present proposal in presence of nonidealities such as the effect of line resistances and transistor threshold voltage variations. Since our proposal preserves the standard 8T-SRAM array structure, it can be used as a storage element with standard read–write instructions and also as an on-demand analoglike dot-product accelerator.

Modeling of FinFET SRAM array reliability degradation due to electromigration

Effective assessment of degradation induced by electromigration (EM) is necessary for the design of reliable circuits based on FinFET technology. In this paper, a new methodology is proposed where FinFET SRAM cell array activity is used to evaluate the resistance degradation due to EM. The implementation of this methodology consists of analysis of stress evolution, a time-dependent resistance model, cell array activity extraction, and a customized algorithm for cell array reliability evaluation. The stress model is derived from the material transport equation which contains the driving forces due to the gradient of vacancy concentration, temperature, hydrostatic stress, and EM itself. The time-dependent resistance shift describes the effect of stress evolution. The customized algorithm is applied to calculate the resistance degradation while considering the characteristics of metal wire arrays in SRAMs. The statistical degradation in a FinFET SRAM cell array reveals that, for the tested case, in addition to the percentage of the workload in various operating modes, the cell array activity distribution also affects EM degradation. More evenly distributed cell activity results in better EM reliability.

Leakage Current Analysis of FinFET Based 7T SRAM at 32nm Technology

FinFETs can be a replacement for bulk- CMOS transistors in many different designs. Its low leakage/standby power property makes FinFETs a desirable option for memory sub-systems. Memory modules are widely used in most digital and computer systems. Leakage power is very important in memory cells since most memory applications access only one or very few memory rows at a given time. As technology scales down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the32nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs efficiency, called variable-supply voltage schemes. In this paper, we’ve illustrated the design and implementation of FinFET based 4x4 SRAM cell array by means of one bit 7T SRAM. FinFET based 7T SRAM has been designed and analysis have been carried out for leakage current, dynamic power and delay. For the validation of our design approach, output of FinFET SRAM array have been compared with standard CMOS SRAM and significant improvements are obtained in proposed model.

Low Power BiCMOS SRAM using 0. 18µm Technology

advances in the field of very large scale system designs brought memory circuits are continuously regulated and in turn, more number of cells could made possible to integrate on small chip. CMOS technology prove boon to memory circuits, which replaced the most of complex circuits to simpler circuits. But the combination of bipolar junction transistors changes the entire scenario. The objective of this paper is to design low power SRAM cell array by using BiCMOS technology. In this paper, BiCMOS technology is used to design SRAM cell using 0.18µm technology. The results are compared with standard 6T SRAM cell. The proposed design results in significant reduction in power consumption as compared to standard 6T SRAM cell and it is verified that the proposed cell can operate at much low supply power with much reduction in power consumption. All the simulation is completed on the Cadence Virtuoso tool. KeywordsSRAM, Standard 6T SRAM, Power Consumption, Power Dissipation and 0.18µm technology.

Design and Implementation of 64-kb CMOS Static RAMs for Josephson-CMOS Hybrid Memories

We are developing a Josephson-CMOS hybrid memory, which enables subnanosecond access time, to overcome a memory bottleneck in single-flux-quantum digital systems. In this study, we designed and examined 64-kb CMOS static RAMs for realizing fully functional hybrid memories. The designed CMOS static RAM is composed of an eight-transistor SRAM cell array, address decoders, and CMOS differential amplifiers. The differential amplifiers can amplify 40-mV input signals from Josephson latching drivers to CMOS voltage levels at high speed. The total number of the differential amplifiers is 21, which are used for an 8-bit word address, a 3-bit block address, 2-bit read/write control signals and 8-bit data inputs. The 64-kb CMOS static RAM was fabricated by using a 0.18 μm CMOS process. We confirmed fully functional read and write operations for all addresses. The access time was evaluated to be 1.34 ns at 4.2 K. The power consumption was estimated to be 27.5 mW for read operation and 41.0 mW for write operation at 1 GHz. The 64-kb CMOS static RAM was combined with a Josephson chip, which includes single-flux-quantum serial-parallel converters and arrays of Josephson latching drivers, with a piggyback configuration. We partly confirmed the correct operation of the 64-kb hybrid memory for limited address.

High Density Low Leakage SRAM Standby Current Reduction with a Channel Stop Implant in p-Type Well in 40nm CMOS Development

In this paper, 32M 0.242 um2 SRAM cell array leakage was reduced significantly by ~ one order of magnitude without affecting the N+/PW junction capacitance after introducing a channel stop implant (CSI) in P-type well. The space for N+ in PW to NW is generally much smaller for SRAM than for logic device, therefore SRAM is normally the weakest point for N+ in PW to NW well isolation. After checking the N+ in PW to NW leakage, we found that its leakage is the dominant factor for the high SRAM standby current. Furthermore, NMOS performance was also improved with this channel stop implant. The N+/PW diode, N+/PW/DNW and P+/NW/PW bipolar were confirmed to be comparable with the baseline without the channel stop implant. P-type well proximity effect (WPE) and NMOS body effect performance were also analyzed.

Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations

Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses.

A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology With Integrated Column-Based Dynamic Power Supply

Column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption.

A 90-nm Low-Power 32-kB Embedded SRAM With Gate Leakage Suppression Circuit for Mobile Applications

In sub-100-nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local dc level control (LDLC) for SRAM cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and fabricated a 32-kB 1-port SRAM using 90-nm CMOS technology. The six-transistor SRAM cell size is 1.25 /spl mu/m/sup 2/. Evaluation shows that the standby current of 32-kB SRAM is 1.2 /spl mu/A at 1.2 V and room temperature. It is reduced to 7.5% of conventional SRAM.

Maximum likelihood estimation for failure analysis [IC yield

This paper presents an iterative maximum likelihood (ML) estimation method for statistical analysis of yield loss. By means of inductive fault analysis (IFA) and circuit simulation, the mapping between defect types to the corresponding fault signature is constructed. Using the count of each fault signature occurrence, which is provided by a tester on defective ICs, the most likely causes of low yield are identified automatically without the need for physically deprocessing the defective IC's. We present an experiment on an SRAM cell array to illustrate the effectiveness of the iterative ML algorithm.