Maximum likelihood estimation for failure analysis [IC yield

Abstract

This paper presents an iterative maximum likelihood (ML) estimation method for statistical analysis of yield loss. By means of inductive fault analysis (IFA) and circuit simulation, the mapping between defect types to the corresponding fault signature is constructed. Using the count of each fault signature occurrence, which is provided by a tester on defective ICs, the most likely causes of low yield are identified automatically without the need for physically deprocessing the defective IC's. We present an experiment on an SRAM cell array to illustrate the effectiveness of the iterative ML algorithm.