SRAM Bit Research Articles

9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage

AbstractWith the development of processes and reduction of transistor size, transistor sensitivity to voltage changes has increased. Traditional SRAM bit cells struggle to function properly at low voltages, and the lengthy write time necessitated by the write conflict problem will inevitably result in write failure. As ultra‐low‐voltage SRAM has emerged as a significant direction of research for SRAM, this paper proposes an ultra‐low‐voltage 9T SRAM bit cell that is conflict‐free. By circumventing write conflicts and enabling rapid writing, the bit cell demonstrates its superiority, particularly at ultra‐low voltages, by eliminating the requirement for peripheral write‐assist circuitry to accomplish chip writing. To assess the performance of the conflict‐free 9T bit cell, simulation experiments are conducted utilizing the 28 nm process model. Simulation results indicate that the 9T bit cell proposed in this paper requires only 66% of the writing time of the traditional 6T cell. This enables the cell to accomplish fast writing and more stable writing performance.

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

As AI models grow in complexity to enhance accuracy, supporting hardware encounters challenges such as heightened power consumption and diminished processing speed due to high throughput demands. Compute-in-memory (CIM) technology emerges as a promising solution. Furthermore, carbon nanotube field-effect transistors (CNFETs) show significant potential in bolstering CIM technology. Despite advancements in silicon semiconductor technology, CNFETs pose as formidable competitors, offering advantages in reliability, performance, and power efficiency. This is particularly pertinent given the ongoing challenges posed by the reduction in silicon feature size. We proposed an ultra-low-power architecture leveraging CNFETs for Binary Neural Networks (BNNs), featuring an advanced state-of-the-art 8T SRAM bit cell and CNFET model to optimize performance in intricate AI computations. Through meticulous optimization, we fine-tune the CNFET model by adjusting tube counts and chiral vectors, as well as optimizing transistor ratios for SRAM transistors and nanotube diameters. SPICE simulation in 32 nm CNFET technology facilitates the determination of optimal transistor ratios and chiral vectors across various nanotube diameters under a 0.9 V supply voltage. Comparative analysis with conventional FinFET-based CIM structures underscores the superior performance of our CNFET SRAM-based CIM design, boasting a 99% reduction in power consumption and a 91.2% decrease in delay compared to state-of-the-art designs.

A single ended, single port configuration based 9 T SRAM cell for stability enhancement

The growing demand for power efficient devices and high-density memories has pushed researchers to develop low power SRAMs. The main objective for these researches is to reduce power consumption and enhances battery life and scaling of technology node. Consequently, in this paper a 9T SRAM bit cell with enhanced stability and single ended, single port configuration is proposed. The cell is designed and simulated at 180 nm technology node with a voltage supply of 1V. The cell proposed has low power consumption owing to single bitline, higher read stability due to isolated read port, better write margin due to disconnected feedback connection and resistant to soft errors because of half select disturbance free architecture. To assess the performance of the proposed cell its performance is compared against existing 6T, 8T, 9TST, SB 9T, TRD 9T, and NTV 9T bit cells. The HSNM (RSNM) and WM values for the proposed cell are equal to 364 mV and 378 mV respectively. The cell is designed to be half select disturbance free and supports bit interleaving. The reliability of the proposed cell is further analysed for local, global and temperature variation. While, the area footprint for the cell is 24.91 μm2.

A Reconfigurable 7T SRAM Bit Cell for High Speed, Power Saving and Low Voltage Application

The decreasing operational voltage and scaled technology node for memory designing has widened the gap between two crucial parameters for an SRAM – delay and power. As the demand for internet of things is increasing, the need for round the clock connectivity is increasing. This mandates designing a cell with a capability to switch between low power and high speed operation. Thus, this paper presents the design of dual mode operational 7T cell that can switch between single port and dual port configuration. The proposed reconfigurable cell can operate as single port or dual port cell single ended 7T cell. The reconfigurability in the cell is realized using control signals. The noise stability of the bit cell is obtained to be 333, 333, and 470 mV for read, hold, and write modes, respectively. The robustness of the cell against temperature variation, process variation and voltage variation is also analyzed. The performance variation in each parameter will not have a dramatic impact as it is within manageable limit. Its write time is 0.14 ns, while 5 ps are required for a successful read operation. The dual port configuration of the cell supports pipelining and thus operates faster than its single port configuration.

A low power single bit-line configuration dependent 7T SRAM bit cell with process-variation-tolerant enhanced read performance

A low power single bit-line configuration dependent 7T SRAM bit cell with process-variation-tolerant enhanced read performance

Optimization of low power 12 T SRAM bit cell using FinFET in 32 nm technology

Optimization of low power 12 T SRAM bit cell using FinFET in 32 nm technology

Analysis and optimization of less power 12 T SRAM bit cell based on FinFET in 32 nm technology

Analysis and optimization of less power 12 T SRAM bit cell based on FinFET in 32 nm technology

Power and Area Efficient 9T CNTFET SRAM Bit Cells with Differential Read Scheme for Low Power Applications

Power and Area Efficient 9T CNTFET SRAM Bit Cells with Differential Read Scheme for Low Power Applications

A Novel Ultra-Low Power 8T SRAM-Based Compute-in-Memory Design for Binary Neural Networks

We propose a novel ultra-low-power, voltage-based compute-in-memory (CIM) design with a new single-ended 8T SRAM bit cell structure. Since the proposed SRAM bit cell uses a single bitline for CIM calculation with decoupled read and write operations, it supports a much higher energy efficiency. In addition, to separate read and write operations, the stack structure of the read unit minimizes leakage power consumption. Moreover, the proposed bit cell structure provides better read and write stability due to the isolated read path, write path and greater pull-up ratio. Compared to the state-of-the-art SRAM-CIM, our proposed SRAM-CIM does not require extra transistors for CIM vector-matrix multiplication. We implemented a 16 k (128 × 128) bit cell array for the computation of 128× neurons, and used 64× binary inputs (0 or 1) and 64 × 128 binary weights (−1 or +1) values for the binary neural networks (BNNs). Each row of the bit cell array corresponding to a single neuron consists of a total of 128 cells, 64× cells for dot-product and 64× replicas cells for ADC reference. Additionally, 64× replica cells consist of 32× cells for ADC reference and 32× cells for offset calibration. We used a row-by-row ADC for the quantized outputs of each neuron, which supports 1–7 bits of output for each neuron. The ADC uses the sweeping method using 32× duplicate bit cells, and the sweep cycle is set to 2N−1+1, where N is the number of output bits. The simulation is performed at room temperature (27 °C) using 45 nm technology via Synopsys Hspice, and all transistors in bitcells use the minimum size considering the area, power, and speed. The proposed SRAM-CIM has reduced power consumption for vector-matrix multiplication by 99.96% compared to the existing state-of-the-art SRAM-CIM. Furthermore, because of the decoupled reading unit from an internal node of latch, there is no feedback from the reading unit, with read static noise, and margin-free results.

Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

AbstractStatic random access memory (SRAM) bit cell is a prominent element for portable devices. The popularity of sleek designs and demand for longer battery life has driven memory cell into nanometer domain. This has also bolstered the need for low‐voltage devices. But reduction in operational voltage for cell is limited by process variation. In this work, a single bit line seven‐transistor (7T) SRAM bit cell is reported. The cell is designed for 32‐nm technology node and is functional at 300 mV. The reported cell maintains a 90‐mV hold and read static noise margins (SNMs), while the write margin is 190 mV. The pulse width needed to successfully write into the cell is 30 ns. The performance of proposed 7T cell is compared against different 6T, 7T, 8T, and 10T SRAM bit cells. The hold and read SNMs for proposed 7T are found to be 58.8%, better than single‐ended 6T cell, while the write ability is improved by 71.4%. The leakage current is observed to have decreased by a factor of 14 for Q = 0 (Q being the data storage node) and by factor of 28 for Q = 1, compared to 6T cell. Also, the area footprint of the proposed 7T SRAM cell is 0.442 μm2.

Analysis of SRAM bit cell topologies in submicron CMOS technology

Analysis of SRAM bit cell topologies in submicron CMOS technology

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V MIN Applications

A 135-Mb 0.021- $\mu \text{m}^{2}$ 6-T high-density SRAM bit cell with write-assist circuitries was successfully implemented by using 5-nm HK-metal gate FinFET with EUV and high-mobility channel (HMC) technology. This article proposes the metal capacitor coupling negative bitline (NBL) and the charge-sharing lower cell-VDD (CS-LCV) write-assist techniques to reduce the SRAM minimal supply voltage. Flying bitline (FBL) architecture is also implemented to improve the high-density SRAM macro-bit density by 5%. Silicon data show that both NBL and LCV write-assist techniques can improve the overall SRAM minimal supply voltage performance by more than 300 mV at the 95th percentile.

A VDD Correction Method for Static Stability Test of SRAM Bit Cell

SRAM stability is a major concern in nanometer CMOS technologies. As the most important metrics of SRAM static stability, the static characteristics of SRAM are derived by static characteristic curves (read butterfly curve, standby butterfly curve, read N curve, write N curve and WNM curve). This paper deduces the read butterfly curve transfer function as an example to show the effect of supply voltage deviation. In order to increase the quantity of SRAM DUTs (Device under Tests) and test accuracy, we propose a test method with VDD correction which eliminates the effect of supply voltage deviation. First, an addressable test structure is applied, where the transmission gates are used to force and sense the node voltages, and then correct the voltages. Second, a test algorithm with fast convergence combining the bisection method and PID (Proportion Integral Differential) algorithm is proposed to correct the voltages. SPICE simulations show that the proposed method reduces the error from approximately 10% (commonly used methods) to less than 2%. It is further implemented in a standard 55nm CMOS process, and the static characteristic curves of 1k-bits SRAM DUTs are measured within the accuracy range of 1 mV, which fit well with the simulation results, indicating the method can accurately measure 1k-bits DUTs.

Variation tolerance for high-speed negative capacitance FinFET SRAM bit cell

Negative capacitance FinFET (NC-FinFET) has a promising developmental prospect due to its superior performance in SS < 60 mV/dec (subthreshold swing), especially in SRAM. Noise margin is an important metric to evaluate the performance for SRAM, together with static leakage, read speed, etc. In this paper, we study the effects of the variation of ferroelectric material (thickness, polarization), FinFET critical physical parameters (fin number, channel length) and some ambient factors (working temperature, supply voltage) on the performance of NC-FinFET SRAM within the reasonable fluctuation tolerance range. The SRAM bit cell is analyzed with a basic 6T structure. The impact of fin number and channel length for NC-FinFET SRAM is different from that of conventional FinFETs. Additionally, the ferroelectric material and some other factors are assessed in detail.

Area-efficient Transposable Crossbar Synapse Memory Using 6T SRAM Bit Cell for Fast Online Learning of Neuromorphic Processors

We present a transposable crossbar synapse memory using 6T SRAM bit cell to speed up online learning of neuromorphic processors at minimal area cost. Based on the proposed integrated transposable row addressing scheme using a row-transition multiplexer, fast write and read operations are made possible for both row-wise and column-wise accesses in an integrated 6T SRAM bit cell array at much smaller area cost compared to the previous works. A 256×256 4-bit transposable synapse memory was implemented in a 28 nm CMOS technology, which had 26% area overhead against the non-transposable 6T synapse memory. The estimated performance gains for unsupervised learning algorithms of spiking neural network and restricted Boltzmann machine using the MNIST data set were 6.3× and 19.3× respectively compared to the non-transposable synapse memory.

Performance Comparison of CMOS and FinFET based Novel 9T SRAM Bit Cell

Performance Comparison of CMOS and FinFET based Novel 9T SRAM Bit Cell

An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis

Performance failure has become a major threat for various memory and analog circuits. It is challenging to estimate the extremely small failure probability when failed samples are distributed in multiple disjoint regions. In this article, we propose an adaptive importance sampling (AIS) algorithm. AIS has several iterations of sampling region adjustments, while existing methods predecide a static sampling distribution. We design two adaptive frameworks based on resampling and population Metropolis–Hastings (MH) to iteratively search for failure regions. The experimental results of the AIS method exhibit better efficiency and higher accuracy. For SRAM bit cell with single failure region, the AIS method uses 2– $27{\times }$ fewer samples and reaches better accuracy when compared to several recent methods. For a two-stage amplifier circuit with multiple failure regions, the AIS method is $90{\times }$ faster than Monte Carlo and 7–23 ${\times }$ over other methods. For charge pump circuit and $C^{2}MOS$ master–slave latch circuit, the AIS method can reach 6– $18{\times }$ and 4– $6{\times }$ speedup over other methods, respectively.

Design and analysis of CMOS based 6T SRAM cell at different technology nodes

The CMOS technology is rapidly growing towards large scale integration on a single chip leading to smaller size consuming smaller area. The demand for speed and efficiency are also increasing day by day. With continues down scaling of technologies, the integral density of the chip increases. Stability and reliability of any memory device such as SRAM, DRAM in different environments, is a critical issue. In this paper, the design and analysis of CMOS based 6T SRAM cell at different technology nodes is demonstrated. The main purpose of this paper is to simulate 6T SRAM to evaluate the performance at different CMOS technology nodes (180 nm, 90 nm, 65 nm, 45 nm) with the help of predictive technology model (PTM) file. The constancy of the SRAM bit cell in terms of static noise margin (SNM) is analysed by butterfly curve method. Simulations are done using BSIM3 model PTM files on HSPICE tool. The results shown in this paper clearly indicate that as we proceed from 180 nm to 45 nm delay reduces and stability improves i.e. read static noise margin (RSNM) is improved by 7.72% while write static noise margin (WSNM) is improved by 5.94% of the 6T SRAM cell.

Low Leakage SRAM Cell with Improved Stability for IoT Applications

Abstract For IoT applications, a new SRAM cell with differential write and single-ended read ability is proposed in this paper. The transmission gate is used as an access transistor to get rail to the rail voltage swing and improved stability. Analysis of leakage power and stability for proposed SRAM cell at supply voltage ranging from 0.9V to 0.5V is compared with the existing 5T and 6T SRAM bit cells at 32nm technology. The transistor stacking effect is used to minimize the leakage current of the SRAM cell. The stability increase is accomplished by isolating read line from the node that causes read disturbance problem. The proposed memory cell shows 436x and 1.15x improvement in read power in comparison to 6T and 5T cell, respectively at 0.8V supply voltage. Stability is also improved by 1.15x and 1.12x at 0.8V of supply voltage.

Design of Self Controllable Voltage Level Circuit SVL for Low Power and High Speed 12t Sram at 15nm Technology

Due to trend of decreasing the device Size and increase in the chip density, the complexity in design increased and it became very complex. The main factor which is main concern in this step is Power dissipation. This can be occurring in many forms like Dynamic, subthreshold leakage and Gate leakage. For every situation the designer has to try to reduce this Power Dissipation factor. In this paper we designed a low power 12T SRAM by using the 15nm technology. SRAMs have large number of applications in high speed registers, microprocessors, small memory banks, general computing applications etc. Therefore delay, power, speed, leakage current and stability are the main concerns. These parameters are in trade off to each other. This paper focuses on the leakage current, power and stability in 12T SRAM bit -cell. We introduce a circuit “self - controllable Voltage Level (SVL)” circuit. The main task of this circuit is to reduce the stand-by leakage power of 12T SRAM. In our Work, We are using the Cadence Virtuoso simulation tool for simulating our circuit. After Comparing our results to the previous methods used for reducing the power leakage we found that there is reduction in average power compare to the previous methods used for power reduction techniques.