SRAM-based Field Programmable Gate Arrays Research Articles

Error Detection Technique for a Median Filter

In digital image processing systems, the acquisition stage may capture impulsive noise along with the image. This physical phenomenon is commonly referred to as “salt-and-pepper” noise. The median filter is a nonlinear image processing operation used to remove this impulsive noise from images. This digital filter can be implemented in hardware to speed up the algorithm. However, an SRAM-based field-programmable gate array implementation of this filter is then susceptible to configuration memory bit flips induced by single event upsets, so a protection technique is needed for critical applications in which the proper filter operation must be ensured. In this paper, a fault-tolerant implementation of the median filter is presented and studied in-depth. Our protection technique checks if the median output is within a dynamic range created with the remaining nonmedian outputs. An output error signal is activated if a corrupted image pixel is detected, then a partial or complete reconfiguration can be performed to remove the configuration memory error. Experimental results show that our technique detects enough corrupted pixels in an image to prevent 91% of the corrupted images from being erroneously sent to the next image processing operation. This high error detection rate is achieved introducing only a 35% of additional resource overhead.

A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

This paper presents a methodology for accurate characterization of Single Event Transient (SET) propagation in SRAM-based Field Programmable Gate Arrays (FPGAs): both generation and measurement of SETs are implemented on chip, respectively connected to input port and output port of the test combinational paths. The scheme we developed is mainly based on two circuits: 1) the one is a SET generating circuit for on-chip producing an adjustable pulse with a temporal resolution of near 100 ps; 2) the other is a SET measuring circuit for on-chip measuring pulses with a temporal resolution of near 80 ps and the ability to detect narrow transient pulses of about 300 ps. Based on above methodology, we investigate the effect of traversing seven logic chains with different gate types and multiple chain lengths on pulse widths, i.e., Propagation Induced Pulse Distorting (PIPD). Results demonstrate, when SETs propagate along Look Up Tables (LUTs) in Virtex-6 FPGAs, there is a broadening for negative SETs (1-0-1) while not for positive SETs (0-1-0); in addition, pulse width has no impact on PIPD, and which is linearly proportional to the number of stages.

Towards an efficient SEU effects emulation on SRAM-based FPGAs

A novel fault injection approach, reproducing results obtained from radiation ground testing while studying the Single Event Upset (SEU) effects on SRAM-based Field Programmable Gate Arrays (FPGAs), is presented. This approach can take into account the relative sensitivity difference between configuration bits set to ‘0’ and those set to ‘1’. According to irradiation experiments conducted under proton beam for a Xilinx Virtex-5 FPGA at the TRIUMF lab, configuration bits set to ‘1’ are approximately twice as sensitive as bits set to ‘0’. This fact was exploited in test sequence generation while performing fault injection experiments, in order to generate more realistic emulation results. The effectiveness of the approach is validated by comparing its results to those obtained with proton radiation tests, for two different ring-oscillator-based experimental setups. It shows that taking this sensitivity into account helps obtain more realistic results while dealing with delays induced by radiation, which justifies considering this relative sensitivity during fault emulation. In fact, comparing the results obtained from the proposed approach to those obtained at TRIUMF gives an absolute relative error of 3.1 and 14%, respectively, for the first and the second setups, while estimating the error between the latter and results from a conventional random fault injection provides error values of up to 75%. Finally, applying our fault injection approach on a more conventional circuit reveals that taking the relative sensitivity difference into account leads to 2.3 times as many errors detected as with random injection. This last result suggests that not taking the relative sensitivity difference into account during emulation can lead to an underestimation of a design sensitivity to radiation.

Racetrack Memory-Based Nonvolatile Storage Elements for Multicontext FPGAs

A multicontext field-programmable gate array (FPGA) is a solution to achieve fast run-time reconfiguration. However, SRAM-based multicontext FPGAs still suffer from high leakage power during sleep, slow power-ON speed, and excessive large memory area. Racetrack memory is one of the most promising resistive nonvolatile memories, with the advantages of low power, high density, and high speed. In this paper, we propose two racetrack memory-based nonvolatile storage elements (NVSEs) for multicontext FPGAs. One is the shifting-based NVSE (type-1) with the advantages of high density and low power. The other one is the address-based NVSE (type-2) with the advantages of high context switching speed and low context switching power. The versatile place and route simulation results show that the type-1 NVSE-based eight-context FPGA reduces the area, critical path delay, and the power of the SRAM-based eight-context FPGA by more than 68.1%, 22.8%, and 13%, respectively. The proposed type-2 NVSE-based FPGAs allow the contexts to be switched 4.46 times faster than the type-1 NVSE-based FPGAs. Both designs improve the FPGA power-ON speed by more than a million times. Compared with the conventional racetrack memory-based lookup table (LUT), the proposed racetrack memory-based LUT may reduce the total power by more than 25%.

Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs

This paper studies the implementation of Double Error Correction Orthogonal Latin Squares (OLS) in Xilinx Field Programmable Gate Arrays (FPGAs). Several existing options to implement the decoder are considered and evaluated. The results show that the decoder complexity can be significantly optimized by appropriately selecting the implementation that is better suited to the internal FPGA structure. A new implementation tailored for the FPGA structure is proposed, which has a more efficient physical resource utilization compared with the existing ones. It is shown that the improvement on resource utilization is also highly correlated with the soft error vulnerability. The proposed decoder scheme has a reduced soft error cross section compared with other implementations. Based on these results, it seems that optimizing the ECC implementation for FPGAs can be effective and may be useful for other codes.

Architecture design for reliable and reconfigurable FPGA-based GNC computer for deep space exploration

SRAM (static random access memory)-based FPGA (field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for SoPC (system on programmable chip) development. However, as the configuration memory and logic memory of the SRAM-based FPGA are highly susceptible to SEUs (single-event upsets) in deep space, it is a challenge to design and implement a highly reliable FPGA-based system for spacecraft, and no practical architecture has been proposed. In this paper, a new architecture for a reliable and reconfigurable FPGAbased computer in a highly critical GNC (guidance navigation and control) system is proposed. To mitigate the effect of an SEU on the system, multi-layer reconfiguration and multi-layer TMR (triple module redundancy) techniques are proposed, with a reliable reconfigurable real-time operating system (SpaceOS) managing the system level fault tolerance of the computer in the architecture. The proposed architecture for the reconfigurable FPGA-based computer has been implemented with COTS (commercial off the shelf) FPGA and has firstly been applied to the GNC system of a circumlunar return and reentry flight vehicle. The in-orbit results show that the proposed architecture is capable of meeting the requirements of high reliability and high availability, and can provide the expressive varying functionality and runtime flexibility for an FPGA-based GNC computer in deep space.

Design and analysis of efficient synthesis algorithms for EDAC functions in FPGAs

Error detection and correction (EDAC) functions have been widely used for protecting memories from single event upsets (SEU), which occur in environments with high levels of radiation or in deep submicron manufacturing technologies. This paper presents three novel synthesis algorithms that obtain area-efficient implementations for a given EDAC function, with the ultimate aim of reducing the number of sensitive configuration bits in SRAM-based field-programmable gate arrays (FPGAs). Having less sensitive bits results in a lower chance of suffering an SEU in the EDAC circuitry, thus improving the overall reliability of the whole system. Besides minimizing area, the proposed algorithms also focus on improving other figures of merit like circuit speed and power consumption. The executed benchmarks show that, when compared with other modern synthesis tools, the proposed algorithms can reduce the number of utilized look-up tables (LUTs) up to a 34.48%. Such large reductions in area usage ultimately result in reliability improvements over 10% for the implemented EDAC cores, measured as MTBF (mean time between failures). On the other hand, maximum path delays and power consumptions can be reduced up to a 17.72% and 34.37%, respectively, on the placed and routed designs.

Validation Techniques for Fault Emulation of SRAM-based FPGAs

A variety of fault emulation systems have been created to study the effect of single-event effects (SEEs) in static random access memory (SRAM) based field-programmable gate arrays (FPGAs). These systems are useful for augmenting radiation-hardness assurance (RHA) methodologies for verifying the effectiveness for mitigation techniques; understanding error signatures and failure modes in FPGAs; and failure rate estimation. For radiation effects researchers, it is important that these systems properly emulate how SEEs manifest in FPGAs. If the fault emulation systems does not mimic the radiation environment, the system will generate erroneous data and incorrect predictions of behavior of the FPGA in a radiation environment. Validation determines whether the emulated faults are reasonable analogs to the radiation-induced faults. In this paper we present methods for validating fault emulation systems and provide several examples of validated FPGA fault emulation systems.

Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

Transistors hit by heavy ions may conduct transiently, thereby introducing transient logic errors. Attackers can exploit these abnormal behaviors and extract sensitive information from the electronic devices. This paper demonstrates an ion irradiation fault injection attack experiment into a cryptographic field-programmable gate-array (FPGA) circuit. The experiment proved that the commercial FPGA chip is vulnerable to low-linear energy transfer carbon irradiation, and the attack can cause the leakage of secret key bits. A statistical model is established to estimate the possibility of an effective fault injection attack on cryptographic integrated circuits. The model incorporates the effects from temporal, spatial, and logical probability of an effective attack on the cryptographic circuits. The rate of successful attack calculated from the model conforms well to the experimental results. This quantitative success rate model can help evaluate security risk for designers as well as for the third-party assessment organizations.

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

AC_ICAP: A Flexible High Speed ICAP Controller

The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.

A Pragmatic Per-Device Licensing Scheme for Hardware IP Cores on SRAM-Based FPGAs

The modus operandi of the upfront intellectual property (IP) licensing model is impractical for the developers of small to medium volume of field-programmable gate array (FPGA)-based applications. The FPGA IP market is in dire need for a more competitive and secure IP licensing scheme to flourish. In this paper, a pragmatic security protocol that could support the licensing of IP cores on a per-device basis without the need for a contractual agreement of an external trusted third party, large bandwidth, and complicated flow of communications is proposed. Besides assuring that the incentives of all stakeholders involved in the FPGA IP core trading are not scarified if not enhanced, the proposed protocol guarantees total secrecy and integrity of licensed IP cores based on available primitives of contemporary SRAM-based FPGA devices. It also prohibits the implementation of protected IP cores on unscreened excess devices and counterfeit chips sold in the gray market. The adoption of IP fingerprinting further deters the IP licensees from abusing the IP cores. Using the self-reconfiguration feature of FPGAs today, the resources consumed by the control module used for the implementation of protected IP cores on the authorized device are temporary and marginal.

IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs

Modern SRAM-based field-programmable gate arrays (FPGAs) are prone to single event upsets compared to application-specific integrated circuits. We propose a synthesis-based in-place x-filling algorithm by utilizing don't cares to augment the reliability of FPGA-based designs. Compared to circuit- and architecture-based solutions, our algorithm is in place, and does not incur area, power, performance, and design time overheads. Compared to other synthesis-based algorithms, we take into account widely accepted interconnect architecture. For the 10 largest combinational MCNC benchmark circuits mapped to 6-LUT architecture, our approach achieves up to 37% greater failure rate reduction, and up to 7 × runtime speedup, compared to the best known synthesis-based in-place algorithm, namely the in-place decomposition algorithm.

A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element

The high leakage current has been one of the critical issues in SRAM-based Field Programmable Gate Arrays (FPGAs). In recent works, resistive non-volatile memories (NVMs) have been utilized to tackle the issue with their superior energy efficiency and fast power-on speed. Phase Change Memory (PCM) is one of the most promising resistive NVMs with the advantages of low cost, high density and high resistance ratio. However, most of the reported PCM-based FPGAs have significant active leakage power and reliability issues. This paper presents a low active leakage power and high reliability PCM based non-volatile SRAM (nvSRAM). The low active leakage power and high reliability are achieved by biasing PCM cells at 0 V during FPGA operation. Compared to the state-of-the-art, the proposed nvSRAM based 4-input look up table (LUT) achieves 174 times reduction in active leakage power and 15000 times increase in retention time. In addition, the proposed nvSRAM-based FPGA system significantly accelerates the loading speed to less than 1 ns with 2.54 fJ/cell loading energy.

Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs

This work investigates the effects of aging and voltage scaling in neutron-induced bit-flip in SRAM-based Field Programmable Gate Array (FPGA). Experimental results show that aging and voltage scaling can increase in at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These results are innovative, because they combine three real effects that occur in programmable circuits operating at ground-level applications. In addition, a model at electrical level for aging, soft error and different voltages in SRAM memory cells was described to investigate by simulation in more details the effects observed at the practical neutron irradiation experiment. Results can guide designers to predict soft error effects during the lifetime of devices operating in different power supply mode.

Analysis of TID Failure Modes in SRAM-Based FPGA Under Gamma-Ray and Focused Synchrotron X-Ray Irradiation

This study investigates the total ionizing dose effect in static random access memory (SRAM)-based field programmable gate array (FPGA). In addition to gamma ray whole-chip irradiation, focused synchrotron x-ray irradiation with beam size of 20 mu m is also used. As a result, the most vulnerable inner circuit in the SRAM-based FPGA is determined directly. Circuit simulation is also executed to understand the failure phenomenon further. The simulated results are consistent with the experimental results.

Hybrid time and hardware redundancy to mitigate SEU effects on SRAM-FPGAs: Case study over the MicroLAN protocol

SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets caused by high-energy space radiation. Single Event Upset (In order to successfully deploy the SRAM-FPGA based designs in aerospace applications, designers need to adopt suitable hardening techniques. In this paper, we describe novel hybrid time and hardware redundancy (HT&HR) structures to mitigate SEU effects on FPGA, especially digital circuits that are designed with bidirectional ports. The proposed structures that combine time and hardware redundancy decrease the SEU propagation mechanisms among the redundant hard units. Analysis results and fault injection experiments on some standard ISCAS benchmarks and MicroLAN protocol, as a case study over the bidirectional ports, show that the capability of tolerating SEU effects in HT&HR technique increases up to 70 times with respect to solely hardware redundant versions. On average, the proposed method provides 39.2 times improvement against single upset faults and 14.9 times for double upset faults; however it imposes about 14.7% area overhead. Also, for the considered benchmarks, HT&HR circuits become 8.8% faster on the average than their TMR versions.

SEU-SECURE PARITY PREDICTION MULTIPLIER ON SRAM-BASED FPGAs

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted effects induced by space radiations especially single-event upsets (SEUs) as soft errors in configuration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-efficient multiplier architecture based on SRAM-FPGA that provides the self-checking capability against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed architecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults.

Compact and Fast Fault Injection System for Robustness Measurements on SRAM-Based FPGAs

Developing safety-aware designs on field programmable gate arrays (FPGA) directly feeds a demand for error emulation techniques. Since for SRAM-based FPGA single event upsets (SEU) are the most important concern, error testing is usually executed using error injection into the configuration memory. This error injection is typically done with either external or internal injection with the corresponding drawback of slow injection speeds or inaccurate results due to injection side effects. In this context, this work introduces a complete test flow with a mathematical framework and injection parameters which allow balancing the tradeoff between quality of the results and injection speed. An implementation of this flow is presented and executed on a case study based on an AES encryption application. The flows implementation has a very low resource overhead, which can be almost negligible in some instances. Therefore, it can be included in a final implementation allowing for robustness measurements of the finally placed and routed design.

Radiation-Hard Field-Programmable Gate Arrays Configuration Technique Using Silicon on Sapphire

Once largely the domain of space-borne applications, the effects of high energy charged particles on electronics systems are now also a concern for conventional terrestrial devices. The configuration memory within reconfigurable components, such as SRAM-based field-programmable gate arrays are particularly vulnerable to radiation-induced single event effects. We present a silicon on insulator (SOI)-based configuration memory system for use in a radiation hard reconfigurable system. A nonvolatile storage cell, able to be manufactured in a standard single polysilicon SOI CMOS process with no special layers, is combined with a Schmitt amplifier, which results in a final structure that exhibits two unique characteristics enhancing its resistance to radiation. First, it is impossible for a radiation-induced event to permanently flip the configuration state. Second, a partial de-programming resulting in a reduction in the magnitude of the storage cell voltage causes a large change in static current that can very easily be detected using a conventional sense amplifier. A simple current detector of the type used in conventional RAM circuits allows the configuration memory to be set up to exhibit self-correcting, or “auto-scrubbing” behavior. Failure estimates indicate a mean time between failures for a single cell to be in the order of 1034 years.