SRAM Array Research Articles

SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability

This paper describes a novel approach to a true random number generator (TRNG) using SRAM circuits. The principles of operation are described in the context of past work on integrated circuit TRNGs. The required modifications to standard SRAM arrays are minor and have little impact on the area. Experimental results from large 1-Mbit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts show good results. Simple helper functions, suitable for very small hardware implementation, allow improvement, including the ability for the resulting binary strings to pass all of the National Institute of Standards randomness tests. We describe the circuits, their principle of operation and statistical behavior, as well as the underlying physical mechanisms providing the entropy.

A continuation approach for computing parameter-dependent separatrices in SRAM cells

• A novel approach to analyze parameter-dependent separatrices in SRAM cells is proposed. • The method is constructed based on boundary-value problems solved via continuation techniques. • In this way, families of separatrices can be approximated in a computationally efficient manner. • The method is tested in a typical SRAM bit cell via the continuation platform COCO. • A comprehensive modelling of the cell is carried out using the EKV equations for CMOS transistors. The continued scaling of CMOS semiconductor technology, together with the corresponding reduction of operating voltages, pose serious challenges for SRAM arrays regarding susceptibility to parameter variations, reduction of stability margins and reliability of read and write operations. One approach, alternative to various noise margin definitions, is to characterize the robustness of SRAM cells via the computation of stability boundaries, also referred to as separatrices. These curves define threshold voltages producing a flip in the logical state of an SRAM cell, which may lead to data loss due to disturbances, e.g. during read operations. The present work proposes a numerical approach to compute families of parameter-dependent separatrices based on path-following (continuation) methods, exploiting the geometric features of one-dimensional stable manifolds around saddle equilibria. The proposed approach is tested on an SRAM cell whose mathematical description is carried out in detail, based on the EKV (Enz, Krummenacher and Vittoz) equations for MOS transistors. In addition, the present work includes a comprehensive numerical study of the effect of parameter perturbations on separatrices, in a computationally efficient manner.

A 64 kB Approximate SRAM Architecture for Low-Power Video Applications

A voltage-scalable SRAM architecture suitable for video applications where energy can be traded with output signal quality is presented. The proposed 6T SRAM architecture uses three supply voltages to improve the static noise margin during read and write modes and also reduces leakage current in retention mode, hence, it allows aggressive supply voltage scaling for low power multimedia applications. Simulation results in IBM/Global Foundries cmos32soi 32-nm CMOS technology show a 69% power saving and a 63% improvement in image quality for the proposed array compared to a conventional single-supply 64-kB 6T SRAM at 0.70 V, 20 MHz. The proposed design also allows a dynamic power-quality tradeoff at run time and makes the 6T SRAM array a suitable power efficient memory for different video/image applications.

Performance Tradeoffs in the Design of Low-Power SRAM Arrays for Implantable Devices

Performance Tradeoffs in the Design of Low-Power SRAM Arrays for Implantable Devices

A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate

The impact of alpha particle and exposure to cosmic radiation has multifold the existing stability issue associated with modern sub-100 nm SRAM cell design. Noise insertion in the half selected cell of a SRAM array is another serious issue which degrades the stability of a cell as well as waste energy through the half selected cells. The proposed highly stable 8T-SRAM cell takes care of both the above mentioned issues effectively. The cell is capable to be arranged in a bit-interleaving fashion which can then use a conventional error correction code (ECC) to correct the single bit error caused by the exposer to cosmic radiation. Traditionally the read stability and write ability are conflicting to each other and any one of them can be enhanced with sacrificing the other. But the proposed cell enhances both the read stability and the write ability simultaneously. Two other cells namely the 8T differential (8T-DIFF) SRAM and 9T read disturbance free (9T-RDF) SRAM are compared with the proposed SRAM cell which consume 20.1% and 16.2% more energy respectively. The read speed of the proposed SRAM is significantly higher than the 9T-RDF SRAM and marginally higher than the 8T-DIFF SRAM. The write speed of the proposed SRAM is also better than the two compared SRAM.

A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array

A multi-functional in-memory inference processor integrated circuit (IC) in a 65-nm CMOS process is presented. The prototype employs a deep in-memory architecture (DIMA), which enhances both energy efficiency and throughput over conventional digital architectures via simultaneous access of multiple rows of a standard 6T bitcell array (BCA) per precharge, and embedding column pitch-matched low-swing analog processing at the BCA periphery. In doing so, DIMA exploits the synergy between the dataflow of machine learning (ML) algorithms and the SRAM architecture to reduce the dominant energy cost due to data movement. The prototype IC incorporates a 16-kB SRAM array and supports four commonly used ML algorithms—the support vector machine, template matching, $k$ -nearest neighbor, and the matched filter. Silicon measured results demonstrate simultaneous gains (dot product mode) in energy efficiency of 10 $\times $ and in throughput of 5.3 $\times $ leading to a 53 $\times $ reduction in the energy-delay product with negligible ( $\le $ 1%) degradation in the decision-making accuracy, compared with the conventional 8-b fixed-point single-function digital implementations.

Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell

Rapid increase in technology is showing a great perception in assessing the complexity of design that can be integrated on a single chip dramatically. Minimum feature sizes, low power consumption, minimum cost and high performance have become the key characteristics of any electronic component. All these factors have plunged the designers into the sub micron space which brings the leakage parameters into forefront. Many electronic components especially digital designs are designed for the storage of data, highlighting the use of memory. So this paper is dedicated to the storage of data by designing 1 KB memory using SRAM. The cell used in implementing the array structure is 7T SRAM with the minimum leakage current 20.16 pA and average delay of 21 ns. This has been done in the form of an array which is a two dimensional structure of basic unit cell SRAM. The array formed in this paper is a squared array of 32 × 32. The other supporting devices in executing this array are address decoder, precharge circuit, write driver circuit and sense amplifiers. The verification of working of 1 KB SRAM array has been done in cadence virtuoso tool in 45 nm technology.

(Invited) Bringing III-Vs into CMOS: From Materials to Circuits

High-mobility channel materials such as InGaAs and SiGe alloys are considered to be the leading candidates for replacing strained Si in future low power/high performance logic circuits. However, the integration of InGaAs on Si and the co-integration of InGaAs devices with SiGe devices are extremely challenging. On the one hand, the large lattice mismatch (8 to 10%) and the potential formation of antiphase domains at the polar/non-polar III-V/Si crystalline interface typically hinder the integration of high quality InGaAs crystals on Si. On the other hand, InGaAs and SiGe require very different processing conditions in terms of thermal budgets, dry and wet chemistries, passivation schemes and contacting schemes which complexifies the realization of CMOS circuits. Recently, tremendous progress were achieved as a result of innovation at the material and device levels. Latest technology developments yielded the first demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si, fabricated with InGaAs selective epitaxy and standard front end of line processes in a 2D co-planar configuration. This novel and scalable CMOS integration scheme enables InGaAs nFET fabrication in close proximity to SiGe pFETs (down to 25 nm spacing), resulting in 6T-SRAM arrays having a minimum cell size below 0.45 μm2. This scheme can be combined with any bulk Si or SOI-based planar or fin technology, and is compatible with standard large-area Si substrate. Furthermore, progress on 3D Monolithic integration showed that this integration scheme not only an opportunity for further density scaling, but it also offers unique advantages for solving the integration of high mobility materials for 3D CMOS and stacking of functional layers on top of standard CMOS circuitry.

In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array

This paper presents a machine-learning classifier where computations are performed in a standard 6T SRAM array, which stores the machine-learning model. Peripheral circuits implement mixed-signal weak classifiers via columns of the SRAM, and a training algorithm enables a strong classifier through boosting and also overcomes circuit nonidealities, by combining multiple columns. A prototype 128 $\times $ 128 SRAM array, implemented in a 130-nm CMOS process, demonstrates ten-way classification of MNIST images (using image-pixel features downsampled from 28 $\times $ 28 = 784 to 9 $\times $ 9 = 81, which yields a baseline accuracy of 90%). In SRAM mode (bit-cell read/write), the prototype operates up to 300 MHz, and in classify mode, it operates at 50 MHz, generating a classification every cycle. With accuracy equivalent to a discrete SRAM/digital-MAC system, the system achieves ten-way classification at an energy of 630 pJ per decision, 113 times lower than a discrete system with standard training algorithm and 13 times lower than a discrete system with the proposed training algorithm.

Monolayer Transistor SRAMs

Monolayer heterojunction FETs based on vertical heterogeneous transition metal dichalcogenides (TMDCFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent subthreshold swing, high I ON I OFF , and high scalability, making them attractive candidates for post-CMOS memory design. This article explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent device modeling with SRAM circuit design and simulation. We perform detailed evaluations of the TMDCFET/BPFET SRAMs at a single bitcell and at SRAM array level. Our simulations show that at low operating voltages, TMDCFET/BPFET SRAMs exhibit significant advantages in static power, dynamic read/write noise margin, and read/write delay over nominal 16nm CMOS SRAMs at both bitcell and array-level implementations. We also analyze the effect of process variations on the performance of TMDCFET/BPFET SRAMs. Our simulations demonstrate that TMDCFET/BPFET SRAMs exhibit high tolerance to process variations, which is desirable for low operating voltages.

A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS

Conventional data-aware structure SRAMs consume unnecessary dynamic power during the read phase due to the read-half-select issue. In this paper, a 9T-based read-half-select disturb-free SRAM architecture with the cross-point data-aware write strategy is proposed. Based on the proposed write-half-select and read-half-select disturb-free strategy, our 9T bitcell structure improves the read and write SNM by 2.5X and 2.4X compared to traditional bitcells. Furthermore, the proposed strategy and 9T bitcell structure can reduce the read power dissipation on bitline of the SRAM array by 5.14X compared with traditional SRAMs. Based on the proposed architecture, a 16Kb SRAM is fabricated in a 130nm CMOS which is fully functional from 1.2V down to 0.33V. The minimal energy per cycle is 11.8pJ at 0.35V. The power consumption at 0.33V is 2.5µW with 175kHz. The proposed SRAM has 1.5X and 4.2X less total power and leakage power than other works.

Bias-Induced Healing of $V_{\text {min}}$ Failures in Advanced SRAM Arrays

A novel bias-induced healing of address specific failing bits in VLSI SRAM functional arrays is demonstrated for the first time in advanced CMOS nodes. Aging effects due to bias temperature instability (BTI) resulting in device shifts are a well-known reliability problem in advanced CMOS technologies. We propose and demonstrate a method of exploiting the BTI mechanism and the addressing capability of SRAM to recover bits that fail during stress. Recovery of failures using this method is demonstrated in both 20- and 14-nm technology nodes in VLSI SRAM arrays. This method introduces the possibility of self-healing SRAM arrays and overcomes many of the limitations of the conventional industry voltage-guard-band approach.

6T SRAM cell analysis for DRV and read stability

The present paper analyzes the hold and read stability with temperature and aspect ratio variations. To reduce the power dissipation, one of the effective techniques is the supply voltage reduction. At this reduced supply voltage the data must be stable. So, the minimum voltage should be discovered which can also retain the data. This voltage is the data retention voltage (DRV). The DRV for 6T SRAM cell is estimated and analyzed in this paper. The sensitivity analysis is performed for the DRV variation with the variation in the temperature and aspect ratio of the pull up and pull down transistors. Cadence Virtuoso is used for DRV analysis using 45 nm GPDK technology files. After this, the read stability analysis of 6T SRAM cell in terms of SRRV (supply read retention voltage) and WRRV (wordline read retention voltage) is carried out. Read stability in terms of RSNM can be discovered by accessing the internal storage nodes. But in the case of dense SRAM arrays instead of using internal storage nodes, the stability can be discovered by using direct bit line measurements with the help of SRRV and WRRV. SRRV is used to find the minimum supply voltage for which data can be retained during a read operation. Similarly, WRRV is used to find the boosted value of wordline voltage, for which data can be retained during read operation. The SRRV and WRRV values are then analyzed for different Cell Ratios. The results of SRRV and WRRV are then compared with the reported data for the validation of the accuracy of the results.

Efficient defect identification of soft failures induced by device local mismatch for nano-scale SRAM yield improvement

As the device size continues shrinking to nano-scale region, tiny defects induced device local mismatch in SRAM array becomes a major yield limiter. It is often quite time consuming and challenging to identify such kind of invisible defects through conventional FA techniques. This paper presents an efficient methodology on device local mismatch fault isolation with the combination of test features, advanced Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) techniques. A successful case study involving this advanced methodology will be also discussed.

A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability

A dynamic threshold voltage control strategy is presented in this paper to minimize leakage power while enhancing the speed and stability. The threshold voltage of driver and access transistor are tuned dynamically through a novel body-bias controller circuit. The word line signal level controls the action of the proposed body-bias controller. In order to reduce subthreshold leakage current, the threshold voltage of NMOS access and driver transistors are adjusted to a high value by applying a reverse body-bias. On the other hand, forward body-bias lowers the threshold voltage of NMOS access transistor thereby enabling faster read and writes operation. Simulation results shows that the proposed design is much better than conventional and other SRAM cells such as, NC SRAM, PP SRAM, WRE8T. The amount of leakage power reduction is as high as 41.071 % over conventional 6T SRAM cell when tested on (8 × 16) SRAM array. Whereas, the improvement in read and write delay is 30 and 15.81 % respectively.

An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies

Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimating yield in large SRAM arrays. Conventional SRAM variability metrics require including test structures that cannot be used to investigate cell bit fails in functional SRAM arrays. This work proposes the Word Line Voltage Margin (WLVM), defined as the maximum allowed word-line voltage drop during write operations, as a metric for the experimental characterization of write stability of SRAM cells. Their experimental measurement can be attained with minimal design modifications, while achieving good correlation with existing writability metrics. To demonstrate its feasibility, the distribution of WLVM values has been measured in an SRAM prototype implemented in 65nm CMOS technology. The dependence of the metric with the width of the transistors has been also analysed, demonstrating their utility in post-process write stability characterization.

Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array

We present an electrical diagnosis methodology for a variety of wearout mechanisms, including back-end time-dependent dielectric breakdown (TDDB), electromigration, stress-induced voiding, gate oxide TDDB, and bias temperature instability, in an SRAM array. First, the built-in self-test (BIST) system detects wearout and identifies the locations of the faulty cells. Next, the physical location of the failure sites within SRAM cells is determined. There are some fault sites for different mechanisms which result in exactly the same electrical failure signature. For these faulty sites, the cause of failure probabilities for each wearout mechanism is estimated by matching the observed failure rate from BIST and the failure rate distribution computed by simulation and as a function of circuit use scenarios. The estimation of wearout distributions is helpful in determining the wearout limiting mechanisms in the field.

Low-power half-select free single-ended 10 transistor SRAM cell

This paper proposes a novel subthreshold 10T SRAM cell. The proposed design removes the half-select issue which is a problem in SRAM array as observed in the case of conventional 6T and 8T cells. Since the proposed cell is free from half-select disturb, bit-interleaving scheme can be implemented. A bit-interleaved architecture helps to reduce errors in multiple bits of a single word. This makes the proposed design immune to soft error caused by α particles or high-energy cosmic rays. The proposed cell uses data-dependent stack PMOS switching scheme (DSPS) to reduce the write access time and improve the write-ability. A single-ended read decoupled scheme used to perform read operation enhances the read stability. Various design metrics of the proposed SRAM cell have been compared with previously proposed cells such as SBI9T, DF9T and UDVS10T. The proposed cell shows 1.07×, 2.89× and 13.78× improvement in write access time while writing ‘0’ as compared to the SBI9T, DF9T and UDVS10T, respectively at a VDD of 0.4 V. The proposed cell shows lesser spread in write delay as compared to DF9T cell, which signifies lower variability. There is 8.4, 10.3 and 6.5 % improvement in WSNM when compared to the three cells mentioned above, respectively. Also, 27.3 and 2.02 % improvements can be observed in RSNM when compared to the SBI9T and DF9T at a supply voltage of 0.4 V. RSNM of UDVS10T is same as that of the proposed design. As far as power consumption is concerned, the proposed design consumes 1.38× lesser read power as compared to UDVS10T and 1.67× and 5.02× lesser write power as compared to DF9T and UDVS10T respectively. The proposed design shows 1.8 % improvement in read current variability when compared to DF9T. Lastly, the proposed cell shows 2.21× and 5.25× higher IREAD/ILEAK as compared to DF9T and UDVS10T.

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization

In sub/near-threshold operation, SRAMs suffer from considerable bitline swing degradation when the data pattern of a column is skewed to ‘1’ or ‘0’. The worst scenarios regarding this problem occur when the currently read SRAM cell has different data compared to the rest of the cells in the same column. In this work, we overcome this challenge by using a column-based randomization engine (CBRE). This CBRE circuit randomizes data stored to SRAM. This makes distribution of “1” and “0” in each column close to 50%, significantly increasing bitline swing. To further improve the bitline swing, we employ bitline boost biasing and dynamic bitline keeper schemes. Based on the mentioned techniques, we fabricated a 256 rows × 128 columns (32 Kb) 8T SRAM array in 65 nm CMOS technology. In our silicon measurement, the SRAM array shows successful 200 mV operation at room temperature, where energy consumption and access time are 1 pJ and 2.5 s, respectively.

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache

In this paper, we investigate the feasibility of voltage adjustment in a large capacity cache, and propose the architecture of voltage-adaptable nonuniform cache access (VANUCA) that exploits near-threshold computing and multivoltage domain to approach the limit of $V_{\rm dd}$ in a low-power cache. However, the adoption of near-threshold voltage (NTV) leads to a rocketing error probability in SRAM arrays, which has to be addressed by effective fault-tolerant techniques. Instead of using error correction code or data duplication, the VANUCA exploits the natural data redundancy across the whole memory hierarchy to enable fast fault recovery in the NTV cache. Based on the discovered data resilience and the multi- $V_{\rm dd}$ architecture, the VANUCA is able to match vulnerable/invulnerable data clusters to available high-/low-voltage domains by utilizing the data migration mechanism in dynamic NUCA. The proposed VANUCA includes two important architectural techniques: 1) static assignment that assumes a fixed voltage domain partitioning and 2) DataMotion that dynamically fits the working set into heterogeneous cache banks through $V_{\rm dd}$ switching. Experimental results show that the VANUCA achieves considerable improvements in energy efficiency over the conventional single-voltage domain NUCA cache.