Squaring Circuits Research Articles

Slew rate enhancement based on use of squaring circuits

A squaring circuit is introduced that boosts the tail current source of an opamp to improve its slew rate. It operates as a differential voltage magnitude detector, which generates opamp tail currents proportional to the magnitude (square) of the opamp's differential input voltage. Experimental results from a fabricated test chip verify current and slew rate enhancement between 900 and 1400% with respect to its initial value with <;20% static current increase.

New Squaring and Square-rooting Circuits Using Cdba

One new squaring and two new square-rooting circuits based on CDBAs have been introduced. The new squarer circuit consists of a CDBA, two NMOS transistors and one resistor. On the other hand, the first square-rooting circuit consists of two CDBAs, two NMOS transistors while the second square- rooting circuit consists of only a single CDBA, two NMOS transistors and two PMOS transistors. The proposed circuits exhibit wide input voltage range, very small error and offer low output impedance to facilitate easy cascading without requiring additional buffers. PSPICE simulation results are included which confirm the practical workability of the new circuits.

CMOS design of a four-quadrant multiplier based on a novel squarer circuit

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a ?3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.

A CMOS current-mode squaring circuit free of error resulting from carrier mobility reduction

This paper presents a new current-mode squaring circuit. The design is based on MOSFETs translinear principle in strong inversion. A new compensation technique to minimize the second order effects caused by carrier mobility reduction in short channel MOSFETs is proposed. Tanner T-spice simulation tool is used to confirm the functionality of the proposed design in 0.18 µm CMOS process technology. Simulation results indicate that the maximum linearity error is 1.2 %; power consumption is 326 µW and bandwidth of 340 MHz.

Multiplier less high-speed squaring circuit for binary numbers

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth’s algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

An approximate logarithmic squaring circuit with error compensation for DSP applications

The squaring function is one of the frequently used arithmetic functions in DSP, so an approximation of the squaring function is acceptable as long as this approximation corrupts the bits that are already corrupted by noise, and does not degrade application׳s performance significantly. Approximation of the squaring function can lead to significant savings in hardware and processing time. Previously proposed approximations of the squaring function include LUT-based solutions, linear interpolation of the squaring function and minimization of combinational logic. This paper proposes approximation based on a simple logarithmic interpolation of a squaring function with a simple logic block, which can be reused for the error compensation. The proposed block performs approximation of the squaring function with a shift operation and a carry-free subtraction. The proposed approximate squarer with one compensation block achieves the average relative error below 1.5% for any bit length, while maintaining a low power consumption. In order to evaluate the device utilization, the propagation delay and power consumption and to compare it with the existing solutions, we have synthesized the proposed squarer and the existing solutions for the standard cell library and 0.25μm CMOS process parameters.

FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS

This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.

An Improved Squaring Circuit for Binary Numbers

In this paper, a high speed squaring circuit for binary numbers is proposed. High speed Vedic multiplier is used for design of the proposed squaring circuit. The key to our success is that only one Vedic multiplier is used instead of four multipliers reported in the literature. In addition, one squaring circuit is used twice. Our proposed Squaring Circuit seems to have better performance in terms of speed.

An analog cell and its applications in analog signal processing

AbstractThis paper presents a straightforward current‐mode CMOS squarer circuit. The proposed circuit exploits the square‐law characteristic of MOS transistor in saturation region. The squarer circuit is then used to implement multiplier and exponential functions. To demonstrate the method, circuits are designed in 0.35 µm CMOS process, using single 3.3 V supply. HSPICE simulations, with level 49 model parameters, confirm the operation of the proposed CMOS circuits. Copyright © 2010 John Wiley &amp; Sons, Ltd.

Multiplier, frequency doubler and squarer circuits based on voltage controlled resistors

In this paper, a floating voltage controlled positive resistor (FVCPR) with its applications is studied in detail. Compared to previously reported resistor topologies consisting of excessive number of CMOS transistors and dissipating much power, the advantages of the FVCPR are to employ only two CMOS transistors in triode region, and to dissipateal most no power when applied input voltage/current is zero. The FVCPR has two control voltages for electronically changing the value of its positive resistance. Also, one of the control voltages can be used to tune the resistive component while keeping the other one constant. A transadmittance-mode (TM) four-quadrant multiplier, a TM sinusoidal frequency doubler and a TM squarer circuit are derived from the FVCPR as application examples. Some time and frequency domain analyses with SPICE simulation program and an experimental test result are included to exhibit the work ability and effectiveness.

Current-mode squaring, square-rooting and vector summation circuits

Abstract This paper presents new current-mode squaring, square-rooting and vector summation circuits based on the second generation current controlled conveyor (CCCII). Consisting of only CCCIIs as active elements not requiring any external passive elements, all of the proposed circuits are capable of high frequency operation and well suited for IC fabrication. Moreover, the circuits performances are insensitive to temperature and their gains can be easily adjusted by varying the input bias current of CCCII. Finally, the simulation results of the proposed squaring, square-rooting and a two-input vector summation circuits are depicted to confirm the theoretical analysis.

A new high speed and low power four-quadrant CMOS analog multiplier in current mode

In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3 V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 μ m standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1 MHz, a - 3 dB bandwidth of 41.8 MHz and a maximum power consumption of 0.34 mW.

Class AB CMOS analogue squarer circuit

CMOS analogue squarer circuit is presented. A compact pseudo-differential pair insensitive to input common-mode variations leads to class AB operation, hence yielding dynamic currents not bounded by quiescent currents. Measurement results for a 0.5 µm CMOS prototype are provided that verify the correct operation of the circuit.

Wide Band Squaring Circuit with Application to Exponential V-l Converter

Wide Band Squaring Circuit with Application to Exponential V-l Converter

Stochastic neural computation. I. Computational elements

This paper examines a number of stochastic computational elements employed in artificial neural networks, several of which are introduced for the first time, together with an analysis of their operation. We briefly include multiplication, squaring, addition, subtraction, and division circuits in both unipolar and bipolar formats, the principles of which are well-known, at least for unipolar signals. We have introduced several modifications to improve the speed of the division operation. The primary contribution of this paper, however, is in introducing several state machine-based computational elements for performing sigmoid nonlinearity mappings, linear gain, and exponentiation functions. We also describe an efficient method for the generation of, and conversion between, stochastic and deterministic binary signals. The validity of the present approach is demonstrated in a companion paper through a sample application, the recognition of noisy optical characters using soft competitive learning. Network generalization capabilities of the stochastic network maintain a squared error within 10 percent of that of a floating-point implementation for a wide range of noise levels. While the accuracy of stochastic computation may not compare favorably with more conventional binary radix-based computation, the low circuit area, power, and speed characteristics may, in certain situations, make them attractive for VLSI implementation of artificial neural networks.

Large signal analysis of low-voltage MOS analogue functional elements using Fourier-series approximations

This paper discusses the large signal performance of low-voltage analogue functional elements built around MOS field-effect transistors (MOSFETs). Fourier-series approximations are obtained for the transfer characteristics of the basic building blocks; such as the balanced source-coupled pair, the unbalanced source-coupled pair with different transistor sizes, the source-coupled pair with bias offset and the squaring circuits. Using the Fourier-series approximations of these basic building blocks, closed-form expressions are obtained for the amplitudes of the harmonics and intermodulation products at the output of analogue functional elements; such as the basic differential pairs, half-wave rectifiers, full-wave rectifiers and multipliers excited by a multisinusoidal input signals. Using these expressions comparison between the large signal performance of analogue functional elements can be performed and the parameters required for a predetermined performance can be determined.

A dual translinear-based true RMS-to-DC converter

A new design technique for a true rms-to-dc converter is implemented around a dual translinear-based squarer circuit. A dual translinear loop and current mirrors are the basic building blocks in this realization scheme, and the computation is carried in current-mode. The conversion circuit consists of a squarer, a low-pass filter and a square-root circuit. Since no rectifier function is required, this converter configuration enables us to obtain a wideband frequency response. The input signal can he voltage or current. In addition, the modification of the converter to construct a vector summation computing circuit is also discussed.

A differential active load and its applications in CMOS analog circuit designs

In this paper we describe a CMOS differential active load and show how it can be used to create various useful structures. Tunable current gain stages and current squaring circuits are discussed. Their connection to a differential pair-based transconductor results in broad-range tunable transconductor structures suitable for adaptive continuous-time filtering applications and a four-quadrant voltage multiplier.

Some circuit design techniques for low-voltage analog functional elements using squaring circuits

This paper describes some novel circuit design techniques for analog integrated circuits operable on low voltage. These techniques make use of squaring circuits as fundamental circuit elements, which can be constructed easily in monolithic form to avoid processing difficulties. The following three circuit design techniques: the transistor-size unbalance technique, the bias offset technique, and the multitail technique, are applied to realize squaring circuits for deriving the inherent exponential law characteristic from a bipolar junction transistor (BJT) and the inherent square-law characteristic from an MOS field-effect transistor (MOSFET). Furthermore, dc transfer characteristics of the fundamental differential pairs, squaring circuits, and some analog functional elements such as OTAs, quarter-square multipliers, and logarithmic IF amplifiers, are verified with transistor arrays and discrete components on a breadboard or implemented with LSI.

A Simple Multiplier and Squarer Circuit

A simple circuit that can be configured either as a two quadrant multiplier or a two quadrant squarer is described. The constant or multiplication/squaring is dependent upon a dc voltage and a pair or resistance-capacitance values. Employing a precision source for the dc voltage and matched resistance-capacitance for the two sets, one can achieve an acceptable level of accuracy. Verification or the feasibility of the circuit configuration is established by way or test results on a prototype.