Split-gate Resurf Stepped Oxide Research Articles

A New Split Gate Resurf Stepped Oxide UMOSFET Structure with High Doped Epitaxial Layer for Improving Figure of Merit (FOM)

The split gate resurf stepped oxide with highly doped epitaxial layer (HDSGRSO) UMOSFET has been proposed. The epitaxial layer of HDSGRSO u-shape metal oxide semiconductor field effect transistor (UMOSFET) has been divided into three parts: the upper epitaxial layer, the lower epitaxial layer and the middle epitaxial layer with higher doping concentration. The research shows that the reduced SURface field (RESURF) active has been enhanced due to the high doped epitaxial layer, which can modulate the electric field distribution and reduce the internal high electric field. Therefore, the HDGRSO UMOSFET has a higher breakdown voltage (BV), a lower on-state specific resistance (RSP) and a better figure of merit (FOM). According to the results of Technology Computer Aided Design (TCAD) simulations, the FOM (BV2/RSP) of HDSGRSO UMOSFET has been improved by 464%, and FOM (RSP × Qgd) of HDSGRSO UMOSFET has been reduced by 27.9% compared to the conventional structure, respectively, when the BV is 240 V. Furthermore, there is no extra special process required in this advanced fabrication procedure, which is relatively cost-effective and achievable.

An Optimized Structure of Split-Gate Resurf Stepped Oxide UMOSFET

In this paper, a split-gate resurf stepped oxide with double floating electrodes (DFSGRSO) U-shape metal oxide semiconductor field-effect transistor (UMOSFET) is proposed. The floating electrodes are symmetrically distributed on both sides of the source electrode in the trench. The performance of the DFSGRSO UMOSFET with different size of floating electrodes is simulated and analyzed. The simulation results reveal that the floating electrodes can modulate the distribution of the electric field in the drift area, improving the performance of the device significantly. The breakdown voltage (BV) and figure of merit (FOM) of the DFSGRSO UMOSFET at optimal parameters are 23.6% and 53.1% higher than that of the conventional structure. In addition, the regulatory mechanism of the floating electrodes is analyzed. The electric field moves from the bottom of the trench to the middle of the drift area, which brings a new electric field peak. Therefore, the distribution of the electric field is more uniform for the DFSGRSO UMOSFET compared with the conventional structure.

Simulation and Result Analysis of Split Gate Resurf Stepped Oxide UMOFSET with Floating Electrode for Improved Performance

In this study, a split-gate resurf stepped oxide with a floating electrode (FSGRSO) UMOSFET has been proposed. The source in the trench is divided into two electrodes, namely: the upper electrode and the lower electrode. The upper one is the floating electrode, which redistributes the electric potential vertically, and improves the breakdown voltage and figure of merit (FOM). The breakdown (BV) and FOM of the FSGRSO UMOSFET have been improved up to 27.3% and 62.7%, respectively, compared with the SGRSO UMOSFET, according to the simulation results.

Way of operation to improve performance for advanced split‐gate resurf stepped oxide UMOSFET

In this study, a way of operating a double split-gate resurf stepped oxide (DSGRSO) UMOS has been proposed. The n-drift region is divided into two parts by the double split-gate: the upper one and the lower one, which enhances the resurf active effect and binges in an electric field peak in the middle of the n-drift region, and decreases the width of split-gate trench, resulting in an increase of figure of merit (FOM). The simulation results show that the DSGRSO UMOS has improved the saturated breakdown voltage by 25.7% and FOM by 108% as compared with SGRSO UMOS at the certain aspect ratio.

Method to improve trade‐off performance for split‐gate power U‐shape metal‐oxide semiconductor field‐effect transistor with compound trench dielectrics

A split-gate power U-shape metal-oxide semiconductor field-effect transistor (MOSFET) with compound trench dielectrics (CTDSG UMOSFET) is proposed. The dielectric layer of CTDSG UMOS is divided into two layers, employing different K values dielectrics for each one. A new electric field peak is generated in drift region. So, a higher breakdown voltage (BV) for devices and a higher doping in the drift region, lower specific on-resistance ( R SP ) can be realised. This work provides theoretical and simulation analyses of CTDSG UMOS device. Compared to split-gate RESURF stepped oxide (SG RSO) UMOS, the BV 2 /R SP of CTDSG UMOS with w = 0.8 μm, L = 6.0 μm and t OX = 0.5 μm is increased by 73% when relative permittivity e 1 = 7.5, 92% when e 1 = 9 and 100% when e 1 = 12. R SP decreases with the increasing of relative permittivity e 1 adopted, when e 1 is less than a certain value.

Split gate resurf stepped oxide UMOSFET with P‐pillar for improved performance

In this work, the authors propose a split-gate resurf stepped oxide with P-pillar (SGRSOP) UMOS structure. The P-pillar trench under the source electrode in SGRSOP U-shape metal-oxide-semiconductor (UMOS) serves the purpose of simultaneously achieving the following: (1) it has formed a local super junction (SJ) structure with the N-type drift. The P-pillar modulates the electric field distribution in the local SJ and increases the N− drift region doping concentration. (2) It has suppressed the parasitic bipolar junction transistor (BJT) effect by adding the P-pillar in the N− drift region, enlarges the boundary of the snapback. As compared with the SGRSO UMOS, the SGRSOP UMOS only add the P-pillar structure, while it has the better performance. The simulation results show that the SGRSOP UMOS reduces the on-state specific resistance (RSP) and increases the transconductance (gm), improves the figure of merit and its UIS ruggedness is as good as that of the split-gate resurf stepped oxide UMOS.

High-Performance Split-Gate Enhanced UMOSFET With p-Pillar Structure

In this paper, a split-gate resurf stepped oxide (RSO) vertical UMOSFET with p-pillar under the p+ plug region structure is proposed. The p-pillar could modulate the electric field of the drift region with the split-gate in 3-D and simultaneously brings electric field peaks at the sidewall junction between p-pillar and n-drift region. Thus the split-gate enhanced with p-pillar (SGEP) UMOS could increase the drift region doping concentration, reduce the on-state-specific resistance, and maintains the breakdown voltage as compared with the super junction and split-gate RSO UMOSs. Numerical simulation results show that the charge imbalance endurance of SGEP is also largely increased.