Split-gate Flash Memory Research Articles

Study and optimize on the process of Floating gate with dry etching

The split-gate flash memory is widely used in the market, and the dry etching process has an important effect on the parameters and performance of the Floating gate. The plasmas containing Cl2 and CF4 were used to etch the top half of polycrystalline gate, and the HBr/He-O2 gases with a high selectivity to oxide were adopted to etch the bottom half. The orthogonal tests were made upon the process parameters and the optimal process parameters of the main etch step were finally determined, and then the final morphology and uniformity of the Floating gate were obtainedwhen adding a proper over etch step.

Localization of NVM Inter-Poly Defects using nanoprobing techniques

The continuous growth and advancements of semiconductor devices for automotive applications and internet-of-things drive the demand and scaling of embedded non-volatile memories (eNVM). Existing eNVM landscape in 40 nm and 28 nm advanced processes is dominated by split-gate flash memory devices (Do, 2016) where inter-poly oxide (IPO) defect is one of the most challenging types of defect to localize (Tan et al., 2019). IPO defects typically surface as full or partial row NVM failures due to globally shared polysilicon select gate, control gate or erase gate among thousands of NVM cells. Conventional NVM bitmap is not effective to isolate these failures. In this paper, a systematic 2 steps isolation approach using nanoprobing techniques is proposed to effectively localize IPO defects. The first step involves the inter-poly leakage characterization to isolate the smallest failure sub-block. The next step utilizes Electron Beam Absorbed Current (EBAC) analysis to effectively localize IPO defect in nanoscale resolution subsequent TEM analysis. Two case studies of split-gate automotive grade eNVM suffering from read/write cycling failure were described to demonstrate the usefulness of the proposed techniques for accurate and precise localization on the NVM IPO defect.

A macro SPICE model for 2-bits/cell split-gate flash memory cell

A SPICE macro-model constructed of 3-series-connected-transistors is proposed to describe the IV behavior of a 2-bits/cell split-gate flash memory cell for the first time. The model features 3 different memory states of the cell, namely ‘11′, ‘10′ and ‘01′ at different temperatures (−40 to 125°C). The cell is constructed of a select-gate transistor in the center with two symmetrical floating gate transistors in two sides. Using the method of capacitive coupling, the model describes the floating gate transistor with BSIM4 (level=54) model with the floating gate voltages changed into a linear combination of the control gate voltage and the select gate voltage. All the BSIM model parameter extraction strategies are applicable for the extraction flow. This novel 2-bits/cell split-gate flash memory cell is fabricated by a 90nm 4-poly 4-metal CMOS process of Shanghai Huahong Grace Semiconductor Manufacturing Corporation.

A Highly Reliable 2-Bits/Cell Split-Gate Flash Memory Cell With a New Program-Disturbs Immune Array Configuration

A highly reliable 2-bits/cell split-gate flash memory cell in a novel program-disturbs immune array architecture is fabricated and demonstrated. Using a novel metal interconnect technique, a new virtual-ground array architecture is realized to greatly improve program disturbs as compared with conventional and-type configuration. A fully self-aligned process with shallow trench isolation in cell array is also proposed for the first time to fabricate this word-line shared split-gate structure without any lithomisalignment issue. Moreover, the negative charge trap in select gate (SG) oxide during conventional poly-to-poly Fowler-Nordheim tunneling erase operation is found as an important contribution to the cycling degradation for cells with thin SG oxide, and a negative control gate bias erase scheme is then presented to enhance the endurance reliability in this paper. A 250-°C baking experiment (before and after cycling) is performed to explore this cell's data retention characteristics, proving the free of extrinsic and intrinsic defect. Erase and program characteristics are comparable with conventional split-gate cell as well.

A novel high-density embedded AND-type split gate flash memory

A new high-density AND-type split gate (ASG) flash memory realized by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm embedded flash process has been successfully demonstrated and fabricated. This ASG flash memory has a pair of symmetric floating gates for performance of 2 bits/cell. By device and process optimization, this cell can operate via highly efficient source side injection (SSI) and Fowler–Nordheim (FN) tunneling mechanisms for program and erase, respectively. Moreover, ASG flash memory significantly shrinks 50% of the unit cell size by sharing word line (WL) and eliminating bit line (BL) contact. Since the ASG flash memory cell and process used are inherited from proven split-gate technology, this work also provides a highly reliable solution for high-density embedded flash application.

Source-side injection single-polysilicon split-gate flash memory

The source-side injection single-polysilicon split-gate NOR (S4-NOR) flash memory is proposed for embedded applications. For the S4-NOR cell, the access and floating gates are patterned on the channel between the source and drain junctions with a gap length of 55 nm using conventional photolithography technology, and the floating gate is capacitively coupled to an n-well memory gate. This technology can improve the compatibility with a single-polysilicon CMOS logic process. The memory cell is programmed within 5 µs with a low drain current of 10 µA, and its program efficiency is insensitive to process parameters except gap length, which are suitable for embedded memories from the process control viewpoint in addition to low power consumption. Good reliability is also realized without the effect of gap oxide leakage. Furthermore, the performance and reliability of the S4-NOR cell can be improved by scaling the logic process without using any special process.

New High-Density Differential Split Gate Flash Memory With Self-Boosting Function

This letter presents a novel high density differential split gate flash memory with self-boosting function realized by 0.18- μm embedded memory technology from Taiwan Semiconductor Manufacturing Company. The cell has a pair of symmetric floating gates to perform differential read for storage electrons in the dual gate. Besides, a simple and nondecoding self-boosting operation is built in to automatically boost threshold levels of the symmetric cells to prevent a long-term charge loss or data degradation problem. Since the cell process and tip erase structure are totally inherited from the proven split-gate flash technology, the highly efficient program and erase performances are remained in the new cell. This implemented self-boosting operation provides a promising solution for reliable embedded memory for advanced CMOS technology.

Non-linear coupling voltage of split-gate flash memory cells with additional top coupling gate

The study presents the dependence of floating gate (FG) coupling potential, V FG on the source line (SL) programming voltage, V SL of the split-gate flash memory cells with an additional top coupling gate above FG, called the `SG-TCG` cells. The mathematical analysis shows non-linear V FG against V SL behaviour of SG-TCG cells depending on the operation region of FG-MOSFETs. It is found that as the value of V SL increases, the value of V FG initially increases steeply, then gradually and finally, linearly with a lower slope. This anomalous V FG against V SL behaviour is because of the potential drop in the bulk of FG-MOSFETs by the applied V SL . The mathematical analysis, also, shows SL coupling factor (κ SL ) roll-off because of the increase in the FG-MOSFETs body potential with the increase in V SL . In addition, κ SL is shown to approach a constant value in the saturation region of FG-MOSFETs where V FG is less susceptible to supply voltage fluctuation. The mathematical analysis agrees very well with the numerical device simulation. The study, clearly, shows that in order to achieve higher shift in programme cell threshold voltage and reduce performance variability owing to supply voltage fluctuation, the target programming bias V SL of nanoscale SG-TCG cells must be higher than the saturation voltage of FG-MOSFETs.

A novel method to improve cell endurance window in source-side injection split gate flash memory

To enhance cell endurance window of a split gate flash memory, we used a ramp pulse with long rising time to replace the conventional square pulse for programming. The change is based on the study of the electric field at electron injection point (EG) related to programming time. Statistic measurements on various samples including different technologies, cell locations (even or odd) and rise times were done. The results confirm that the read currents shift under erase state (ΔIr1) could be improved significantly with an acceptable programming speed by the proposed method.For example, as increasing the rising time from 0.1μs to 20μs for the conventional square pulse and the ramp pulse respectively, after 1M cycling the ΔIr1 is reduced from 64.8% to 36.2% with an acceptable minimum programming time of 12.5μs.

Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory

The impacts of different source junctions on the program/erase speed and cycling degradation are studied in details for split-gate memory using source-junction-side FN erase and source-side injection program. The device with pure phosphorous source junction has faster program but slower erase speed than that with phosphorous plus arsenic source junction, mainly because of stronger coupling between floating gate and pure phosphorous junction. During program/erase cycling, the memory cell with phosphorous junction shows much higher program-VT rise but less erase-VT increase than that with phosphorous-plus-arsenic junction. For the phosphorous junction, it is found the cycling-induced damage is mainly caused by program operation near the injection point. For the phosphorous-plus-arsenic junction, however, program and erase generate almost equal amount of damage near the injection point and the source junction, respectively. Anneal after phosphorous-plus-arsenic implant improves cycling performance due to less abrupt junction.

Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

The erase voltage impact on the 0.18 μm triple self-aligned split-gate flash endurance is studied. An optimized erase voltage is necessary in order to achieve the best endurance. A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop, which is induced by tunnel oxide charge trapping during program/erase cycling. A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping. A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.

A destructive evolutionary algorithm process

This paper describes the application of evolutionary search to the problem of flash memory wear-out. Flash memory differs from standard RAM in that it can wear out due to the manner in which it is programmed. The operating parameters, such as voltage levels, of flash memory are notoriously difficult to determine, as the optimal values vary from batch to batch. The current method in use is an expensive and time-consuming manual process of destructive testing. Understandably, this process is normally undertaken only at design time and testing on individual batches is normally not feasible. The results are sub-optimum solutions which do not minimise wear-out over the lifetime of the device. This is an enormously important issue in manufacturing, as most Flash Memory devices requiring reliability (e.g. solid state device disk drives) often have 100% or more redundancy to compensate for the wear-out rates. We establish the viability of a hardware platform that utilises an Evolutionary Algorithm to perform destructive experimentation on hard silicon in order to discover optimal or, at least favourable, operating parameter settings automatically in a manufacturing environment. Here, we describe this hardware and reveal results demonstrating an average life extension of between 250 and 350% over the factory set conditions with a maximum life extension exhibited of 700% all for cells within the same device over the factory settings. Furthermore, since the process is automated, it is possible to leverage the spread between process batches to further enhance device specifications, facilitating the near no-cost life extension of a split-gate flash memory device.

The split-gate flash memory with an extra select gate for automotive applications

In this paper, novel split-gate flash memory with an extra select gate (ESG) to improve the operation window has been investigated in details. Experimental results show that with the ESG (called 2.5T cell), the cell showed a better program wordline disturb window than that of the traditional split-gate flash memory cells (called 1.5T cell) around 0.5 V (at V s = 10 V). The offset of minimum drain voltage to avoid punch through disturb between without and with wordline stress for 2.5T cell and 1.5T cell are around 0.05 V and 0.2 V, respectively. We attribute these improvements in wordline disturb behaviors to the reduction of channel leakage current with the addition of ESG. During the erase stage, the gate oxide of the ESG suffers free stress, thus having better oxide integrity to resist the generation of channel leakage current. In addition, the ESG offers a reverse bias to retard the leakage current from drain to source.

A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme

Replica-cell sensing schemes are commonly used in the read circuits of flash memories to provide the appropriate reference current across various process, voltage and temperature (PVT) conditions. However, process variation on the replica array causes fluctuations in the settling time and the value of the reference current across dies or wafers, especially in split-gate flash memories. A long settling time of reference current slows down the access time, and causes ringing on outputs. Fluctuation in the reference current produces various sensing margins, and decreases the yield, due to tail bits. A circuit-level technique for embedded flash memories, called pre-stable current sensing (PSCS), is proposed to reduce the fluctuation in access time and sensing margin, without additional masks or process steps. Experiments on fabricated flash macros (4 Mb, 2 Mb, 1 Mb, and 512 Kb) using a 0.25 mum embedded flash process demonstrate that PSCS achieves uniform access time across hundreds of samples. Additionally, PSCS works with a wide range of supply voltages (1.1-3 V).

High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory

This work proposes a novel p-type boron-doped floating gate for n-channel split-gate flash memory. A lower program voltage, with a programming time of 7 μs, results in five times of the conventional source-side injection programming efficiency, a 5% wider program/erase window, and more reliable endurance characteristics. Additionally, a 2 Mbit embedded flash Intellectual Property (IP) has been successfully implemented and statistically compared. The lower program voltage reduces concerns around the high-voltage decoder, the charge pump efficiency, and the array efficiency beyond 90 nm nodes. The new p-doped split-gate structure provides a very promising solution for advanced embedded split-gate flash memory beyond the 90 nm node.

Scaling considerations for sub-90 nm split-gate flash memory cells

A systematic methodology is presented to scale split-gate (SG) flash memory cells in the sub-90 nm regime within the presently known scaling constraints of flash memory. The numerical device simulation results show that the high performance sub-90 nm NOR-type SG cells can be achieved by a suitable channel and source-drain engineering. An asymmetric channel doping profile along with ultra-shallow source-drain junctions was used to achieve the target drain programming voltage (V sp ) for an efficient cell programming while keeping the cell breakdown voltage, BV > V sp , with tolerable leakage currents. The study shows that with properly optimised technology parameters, 65 nm SG-NOR flash memory can be achieved with an adequate cell read current, a tolerable programmed cell leakage current at the read condition and efficient write and erase times.

Design Considerations for Sub-90-nm Split-Gate Flash-Memory Cells

This paper presents a systematic methodology to design efficient sub-90-nm split-gate Flash-memory cells and optimize the cell performance within the presently known scaling constraints. The device-simulation results show that the high-performance sub-90-nm split-gate cells can be realized by a proper optimization of the channel and asymmetric halo-doping profiles and shallow source/drain junctions. In this paper, the halo-and channel-doping profiles were optimized to achieve the target drain-programming voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> = 6.5 V for an efficient cell programming, whereas keeping the breakdown voltage BV > V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> with tolerable leakage currents. It is shown that, using the properly optimized technology parameters, 65-nm split-gate Flash memory can be achieved with cell-read current, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r1</sub> ap 235 mum, programmed cell-leakage current, Ir <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> < 2.2 nA/ mum at the read condition, time-to-program ap 30 mus, and time-to-erase ap 40 mus. This paper clearly demonstrates the feasibility of high-performance 65-nm split-gate Flash-memory cells.

Efficient Low-Temperature Data Retention Lifetime Prediction for Split-Gate Flash Memories Using a Voltage Acceleration Methodology

In developing a fast statistical testing methodology to predict the postcycling low-temperature data-retention lifetime of split-gate Flash memories, word-line stress is used to accelerate the charge-gain effect responsible for bit-cell-current reduction among the tail-bits. To find out the voltage dependence on data-retention lifetime, various word-line stress voltages are performed to enhance the charge-gain effect of the erase-state cells. At an accelerated state, word-line stress lifetime tests can be completed within a much shorter test period and still provide accurate lifetime prediction for embedded Flash-memory products

Statistical Modeling for Postcycling Data Retention of Split-Gate Flash Memories

In developing an accurate lifetime-prediction model for postcycling data-retention failure rate of split-gate Flash memories, a floating-gate potential extraction method from the measured bit-cell-current data is proposed. Stress-induced leakage current through the coupling oxide caused by the source-side channel hot electron injection during program operation is the major cause for postcycling data-retention failure bits. Considering charge conservation and trap-assist-tunneling leakage current, the charge-gain behavior under low-temperature bake is modeled and the failure rate under various measured conditions can be predicted precisely. We have found that data-retention lifetime decreases as program/erase (P/E) cycling increases, while failing bits increase with numbers of P/E cycling.

A novel self-aligned highly reliable sidewall split-gate flash memory

A self-aligned sidewall split-gate Flash memory cell is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The unit cell size of 12.7 F/sup 2/ (F is the feature size), formed in a 32-Mb NOR architecture, and the acceptable erase speed of 20 ms for block erase (512 K bits, 16 pages) are quite competitive. Endurance cycles up to 10/sup 5/ confirm the novel cell to be highly reliable as compared with the conventional source-side erase scheme. The bake experiment at 250/spl deg/C before and after program/erase cycles indicates the cell not only free of extrinsic defects in the manufacturing process but also experiencing excellent retention characteristics. Disturb effects during the programming and read-out operations are examined in detail and the operating conditions for disturbs inhibition are readily determined. We eventually elaborate on the differences between the proposed cell structure and existing ones, as well as on the NAND architecture application.