Split-drain Magnetic Field-effect Transistor Research Articles

Compact modeling of sectorial split-drain magnetic field-effect transistors

Split-drain magnetic field-effect transistor (SD-MAGFET), having the key advantage of possible system integration with the mainstream CMOS technology, should be one of the key technological options for achieving better human and environmental interfacing of digital products as proposed in the More-than-Moore paradigm. However, the characteristics, the potential, and the design methodologies of this new device structure have not fully explored yet. By introducing the effective channel width concept and basing on the first principle of charge transport, we conducted a compact modeling on the magnetic sensitivity of sectorial split-drain MAGFET (SSD-MAGFET). Our model provides some intuitive views on the effects of the devices parameters, such as the sectorial angle, gap width between the two drains, effective aspect ratio, on the operation range and magnetic sensitivity. The model agrees well with the experimental results and suggests that the sensitivity-B field relationship could be approximated by two piecewise linear regions according to the field strength and there exists an optimal sector angle which is governed by the gap width and effective aspect ratio of the SSD-MAGFET.

Research of Magnetic Characteristics of the Split-Drain MAGFET Based on Nano-Polysilicon TFTs

The split-drain magnetic field effect transistor (MAGFET) based on nanopolysilicon thin film transistor (TFT) is fabricated on <100> high resistivity silicon substrates by (complementary metal oxide semiconductor) CMOS technology in this paper. It contains source (S), drain1 (D1), drain2 (D2) and gate (G), and adopts nanopolysilicon thin films and nanopolysilicon/high resistivity silicon heterojunction interfaces as the magnetic field sensing layers. The influence of the channel size and shapes on the transistor, are studied to further improve its magnetic sensitivity. When the ratio of channel length and width (L/W) of MAGFET is 80 μm/160 μm, VDS=5.0 V, the MAGFET with convex channel has higher magnetic sensitivity than the rectangle and concave, the absolute current magnetic sensitivity SI and the absolute voltage magnetic sensitivity SV of the proposed sensor reach the maximum values, and are 0.021 mA/T and 55 mV/T, respectively.

Fabrication and characterization of the split-drain MAGFET based on the nano-polysilicon thin film transistor

A split-drain magnetic field-effect transistor (MAGFET) based on a nano-polysilicon thin film transistor (TFT) is proposed, which contains one source, two drains and one gate. The sensor chips were fabricated on (100) high resistivity silicon substrate by CMOS technology. When drain—source voltage equals 5.0 V and length and width ratio of the TFT channel is 80 μm/160 μm, the current and voltage magnetic sensitivities of the split-drain MAGFET based on the TFT are 0.018 mA/T and 55 mV/T, respectively. Through adopting nano-polysilicon thin films and nano-polysilicon thin films/high resistivity silicon heterojunction interfaces as the magnetic sensing layers, it is possible to realize detection of the external magnetic field. The test results show that magnetic sensitivity of the split-drain MAGFET can be improved significantly.

Thermal stability of sectorial split-drain magnetic field-effect transistors

The effect of charge trapping on the performance of sectorial Split-Drain Magnetic Field Effect Transistor (SD-MAGFET) under the influence of magnetic field is examined based on conventional capacitance measurement techniques upon different magnetic field strength and thermal conditions. The experimental results confirmed the charge trapping effect in sectorial SD-MAGFET is magnetic field and temperature dependent, where the charge trapping sites are localized at the channel boundary, which verifies the conjecture of trap-assisted magnetic sensitivity hysteresis and deterioration of the device found in recent literatures. The results of the study are useful to sectorial SD-MAGFET in high performance magnetic sensing applications.

CMOS magnetic sensor integrated circuit with sectorial MAGFET

In this paper, a CMOS magnetic sensor integrated circuit (IC) for a perpendicular magnetic field is introduced. The sensor integrated circuit is designed and fabricated in a 0.6 μm digital CMOS process. It consists of a pair of common-source split-drain magnetic field-effect transistor (MAGFET), a pre-processing circuit with a switches array, a correlated double sampling (CDS) circuit and a digital controlling part. The measurements of perpendicular magnetic field as well as the noise shaping are realized on-chip by the two functioning modes of the sensor integrated circuit. The MAGFET is sectorial with a radius of 48 μm and an angle of 90°, and the measured sensitivity S A (current-related sensitivity) is 3.61%/T. At the working frequency of 10 kHz, the sensitivity of the magnetic sensor is 2.62 V/T.

Sector split-drain magnetic field-effect transistor based on standard CMOS technology

A novel sector split-drain magnetic field-effect transistor (MAGFET), which is compatible with standard 0.6 μm N-well CMOS technology, has been suggested and an analytical model of the sector MAGFET is also developed. The model of sector MAGFET is focused on the effect of primary geometric parameters to sensor sensitivity. In order to verify the advantage of the sector MAGFET, the sector structure is also compared with traditional rectangle structure by the simulations and the experiments. The maximum sensor sensitivity of 3.77%/ T of the sector MAGFET is obtained by the experimental results and improvements of sensitivity are attributed to sector structure.

Weak magnetic field pattern detection by CMOS magnetic latch

A CMOS magnetic latch for digital magnetic field detection is reported. It is based on a single split-drain magnetic field-effect transistor with a positive feedback imported by a pair of lateral floating gates. The magnetic latch achieves its maximum magnetic sensitivity when latch-up takes place. A linear equation is used to model the positive feedback and the latch-up process. By imposing a reset-evaluation mechanism, the magnetic latch is evaluated for digital magnetic pattern detection. Experimental results show that the minimum detectable magnetic flux density for the magnetic latch could be down to less than 0.1 mT with low bit error rate.