Split Capacitor Array Research Articles

A calibration-free 10.7 fJ/conv.-step 12-bit 120-MS/s pipelined SAR ADC in 40nm CMOS

A calibration-free 12-bit 120-MS/s 2-stage pipelined successive approximation register (pipelined SAR) analog-to-digital converter (ADC) is presented in this paper. In asynchronous SAR ADCs, capacitive digital-to-analog converters (CDACs) are designed with bottom-plate sampling to improve sampling accuracy and split-capacitor array to save switching energy. Furthermore, both reference scaling technique and a PVT-stabilized closed-loop residue amplifier are implemented in this design to obtain an accurate inter-stage gain, enabling no additional calibration required in the pipelined SAR ADC. The prototype ADC in 40nm CMOS technology achieves a peak signal-to-noise-distortion ratio (SNDR) of 73.4 dB and 88.91dB spurious-free-dynamic-range (SFDR) at 120 MS/s sampling rate, consuming 4.88 mW power from 0.9 V supply voltage, and corresponding to an excellent figure-of-merit (FoM) of 10.7 fJ/conv.-step.

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs

Process variations and the effect of interconnect parasitics can cause significant perturbations in the performance metrics of capacitive digital-to-analog converters (DACs). This paper develops fast constructive procedures for common-centroid placement and routing for binary-weighted and split capacitor array topologies of charge-sharing DACs. Our approach particularly targets FinFET technologies with high wire and via parasitics: in these technology nodes, we show that the switching speed of the capacitor array, as measured by the 3dB frequency, can be severely degraded by these parasitics, and develop techniques to place and route the capacitor array, for both binary-weighted and split DACs, to optimize the switching speed. A balance between 3dB frequency and DAC INL/DNL is shown by trading off via counts with dispersion. The approach delivers high-quality results with low runtimes.

A 9-bit 8.3 MS/s column SAR ADC with hybrid RC DAC for CMOS image sensors

This paper presents a synchronous 9-bit column successive approximation register (SAR) ADC for CMOS imaging sensors. The SAR ADC uses a pseudo-differential RC DAC and a split capacitor array to reduce power consumption and chip area. To improve the sampling rate and accuracy of the column ADC, a dynamic comparator consisting of a two-stage preamplifier and a latch, as well as the output offset storage (OOS) technique is adopted. Based on a 180 nm standard CMOS technology, the presented SAR ADC was taped out and verified. The test results show that the designed SAR ADC achieves the SFDR of 64.54 dB, the ENOB of 8.35 bits, and a power consumption of 0.5 mW with FOM of 235 fJ/conversion-step at 8.3 MS/s sample rate under 1.8 V power supply. The proposed SAR ADC is very suitable for the readout circuit interface of large-scale imaging sensors.

A 12bit 250 MS/s 5.43fJ/conversion-step SAR ADC with adaptive asynchronous logic in 28 nm CMOS

A 12-bit 250-MS/s adaptive asynchronous successive approximation registers analog-to-digital converter (SAR ADC) with a Non-binary segmented split capacitor array is proposed. The Non-binary bridge split capacitor array leads to much larger units with reduced total capacitance and allows for reducing digital-to-analog converter (DAC) settling time and power consumption. The reset time of the comparator is automatically and precisely adjusted according to the settling time required by each capacitor of the non-binary capacitor array, which accelerates the ADC quantization. With the proposed adaptive asynchronous logic (AAL), the settling time utilization will reach 98.6% and the overall ADC's speed can be increased by 30%. The circuit was designed in 28 nm CMOS technology. The mismatch of the capacitor is calibrated by the Least Mean Square (LMS) background calibration for high speed and low power consumption. Based on post-layout simulations, the ADC achieves a signal-to-noise distortion ratio (SNDR) of 67.92 dB at 250 MS/s sampling rate and consumes 2.76 mW, resulting in a figure of merit of 5.43fJ/conversion-step. The ADC core occupies an active area of only 100 μm × 350 μm.

A novel noncoupling capacitor split capacitor array structure for high resolution SAR ADC

In order to achieve high resolution in Successive Approximation Register (SAR) Analog to Digital Converter (ADC), a novel noncoupling capacitor split capacitor array structure is proposed, which solves the coupling capacitor mismatch problem in the traditional split capacitor array structure. This paper analyzes the structure and its capacitor array mismatch. Based on the structure and analysis, a 12-bit SAR ADC is designed and implemented in GSMC 0.11 [Formula: see text]m CMOS process. The measured results show that the Signal to Noise Ratio (SNR) is 72.61 dB and Effective Number Of Bits (ENOB) is 11.77 bit, which prove the advantages of this structure in the design of high resolution SAR ADC.

A 28 nm CMOS 10 bit 100 MS/s Asynchronous SAR ADC with Low-Power Switching Procedure and Timing-Protection Scheme

This paper presents a 10 bit 100 MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS) applications. Several techniques are adopted in the proposed switching procedure to achieve better linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number of capacitors; a parallel split capacitor array in combination with a partially thermometer coded technique can minimize the switching energy, improve speed, and decrease differential non-linearity (DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured DNL and integral non-linearity (INL) without calibration are +0.37/−0.44 and +0.48/−0.63 LSB, respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 35.6 fJ/conversion-step.

A novel split capacitor array switching scheme with proportional coefficient for SAR ADC

A novel switching scheme with proportional coefficient for successive approximation register analog-to-digital converter is presented in this work. The proposed switching scheme realize proportional coefficient by means of charge-sharing, which can achieve a high energy efficiency. Due to the split capacitor array structure is adopted here, the total capacitance can be reduced by 96.9% over the conventional structure. Moreover, the bridge capacitor is the unit capacitor, which is very convenient for layout design and capacitance matching. Furthermore, the proposed switching scheme reduces the energy by 99.9% compared with the conventional architecture through using the MSB-split switching structure and the single-side method. The proposed switching scheme also has a good performance in reset energy consumption and linearity. Based on the MATLAB simulation results, the maximum differential nonlinearity and maximum integral nonlinearity results of the proposed switching scheme are 0.626 LSB and 0.727 LSB, respectively.

10-bit Single-Slope ADC with error quantification and double reset technique for CMOS image sensor

In this paper, a digital correlated double sampling (CDS)-based 10-bit Single-Slope Analog-to-Digital Converter (SS ADC) with error quantification and double reset technique for CMOS image sensor is proposed. The SS ADC circuit block contains a ramp generator, parallel counters and comparators. The error quantification (EQ) technique is adopted to reduce the clock numbers that are counted in the digital counter and the power consumption during the whole digitizing process. To improve the speed of this SS ADC, the double reset technique is introduced to complete the whole digital CDS (DDS) operation with one ramp, and 256 clocks are saved compared with the conventional one. The Digital-to-Analog Converter (DAC) used in the ramp generator is based on the split-capacitor array with a redundant capacitor, and its linearity performance with capacitor mismatch is analyzed to make the distribution of bits in MSB and LSB arrays. The proposed SS ADC is implemented and simulated through 130 nm process. Under the dark (pixel level is 0.1 V) and bright (pixel level is 1.2 V) condition, the column FPN of 0 LSB and 9.8 LSB are achieved in the readout circuit, and 58.7% and 23.6% of power consumption is saved in the hybrid digital counter, respectively.

An energy efficient SAR ADC with lowest total switching energy consumption

A new capacitor switching scheme with considerable energy saving for successive approximation register (SAR) analog to digital converter (ADC) is presented. Employing different switching sequence and also one switching event in a cycle in this technique, result in 97.67% reduction in switching energy. Besides that, in the proposed method, an 8 × reduction in total capacitance compared to the conventional architectures achieved by benefiting from LSB split capacitor array. Furthermore, the proposed technique shows the minimum power dissipation in driving the switches since it has only one switching event per cycle and lowest capacitor array compared to the other techniques. Employed the proposed switching scheme, a 10-bit 1-kS/s SAR ADC is designed in 0.18-µm CMOS technology with an active area of 0.025 mm2. With a 1-V power supply for analog and 0.5-V for digital circuit, the ADC achieves an ENOB of 9.73 bits and a FoM of 4.1 fJ/conversion-step. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed.

Calibrated 10 b 28 nm CMOS SAR ADC based on integer‐based split capacitors

A calibrated 10 b 5 MS/s 28 nm CMOS successive-approximation-register ADC based on an integer-based split capacitor array is presented. The proposed ADC employs a split capacitor array to optimise the overall power consumption, chip area and linearity performance. An attenuation capacitor between two capacitor arrays is implemented with an integer multiple of unit capacitors rather than a fraction of unit capacitors. The proposed calibration of capacitors reduces the non-linearity error caused by device mismatches in the conventional split capacitor array. The measured prototype ADC which has an active die area of 0.063 mm2 shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 59.25 and 70.44 dB, respectively, and consumes 42.5 μW at 0.7 V and 5 MS/s. Moreover, the measured differential non-linearity (NL) and integral NL are within 0.36 and 0.52 least significant bit, respectively, after calibration.

High-resolution 1 MS/s sub-2 radix split-capacitor SAR ADC

This paper proposes a high-resolution successive-approximation register (SAR) analog-to-digital converter (ADC) with sub-2 radix split-capacitor array architecture. The built-in redundancy of sub-2 radix architecture provides additional information in the digital calibration based on offset double injection. The calibration method is simple in structure and fast in convergence. The correction of errors in each bit is independent of those in the previous bit. A split-capacitor array is used to reduce the total capacitance especially in a high-resolution SAR ADC. An offset signal is injected by the switching scheme of capacitor array to minimize the hardware overhead. The prototype of 0.18 μm CMOS process obtains 14.46 bit ENOB and 95.65 dB SFDR after calibration. With calibration, the INL and DNL are −0.813/0.938 and −0.625/0.688, respectively.

Linearity analysis of single-ended SAR ADC with split capacitive DAC

This paper proposes the design of a 6-bit single-ended SAR ADC with a variable sampling rate at a maximum achievable speed of 50 MS/s. The SAR ADC utilizes the split capacitor array DAC with a non-conventional split-capacitor value. The influence of switches in the capacitive DAC on the ADC's non-linearity is analysed. According to the fulfilled analysis the recommendations for switches and capacitor array dimensioning are given to provide a minimum differential non-linearity (DNL).At a sampling rate of 50 MS/s, the SAR ADC achieves an ENOB of 5.4 bit at an input signal frequency of 1 MHz and consumes 1.2 mW at a 1.8 V power supply, resulting in an energy efficiency of 568 fJ/conv.-step. The SAR ADC was simulated with parasitics in a standard 180nm CMOS process.

High efficiency two-step capacitor switching scheme for SAR ADC

A high efficiency two-step capacitor switching scheme for a successive approximation register analogue-to-digital converter is presented. Two-step architecture, split capacitor array, C-2C dummy capacitor and multiple switching schemes are combined in the proposed switching scheme. The proposed switching scheme achieves a 99.75 % reduction in switching energy and the total capacitance is reduced 85.9 % compared with the conventional architecture.

Low power Analog Digital Converter for a silicon photomultiplier readout ASIC

We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end ``KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit ADC resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block is used to minimize the required sampling rate. We present design details and simulation results of the ADC, as well as the peak sensing track & hold circuit.

An 8-bit 500-MS/s asynchronous single-channel SAR ADC in 65 nm CMOS

This paper presents an 8-bit 500-MS/s asynchronous single-channel successive approximation register analog-to-digital converter (SAR ADC). A split capacitor array technique is applied to decrease t...

A 0.8-V, 1-MS/s, 10-bit SAR ADC for Multi-Channel Neural Recording

This paper presents a 10-bit single-ended SAR ADC suitable for multi-channel neural recording. The proposed ADC introduces several power saving techniques to boost the energy efficiency. The ADC is built with on-chip common-mode buffer for input tracking, which is reused as the pre-amplifier of a current-mode comparator during conversion. A small capacitor is inserted between the amplifier and the capacitive DAC array in order to reduce the capacitive load on the amplifier. A split capacitor array with dual thermometer decoders is proposed to reduce the switching energy. Implemented in 0.13-μm CMOS technology, the ADC achieved a maximum differential nonlinearity (DNL) of -0.33/+0.56 LSB, maximum integral nonlinearity (INL) of -0.61/+0.55 LSB, effective number-of-bits (ENOB) of 8.8, and a power consumption of 9-μW.

A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors

This work proposes a 12 b 10 MS/s 0.11 μm CMOS successive-approximation register ADC based on a C-R hybrid DAC for low-power sensor applications. The proposed C-R DAC employs a 2-step split-capacitor array of upper seven bits and lower five bits to optimize power consumption and chip area at the target speed and resolution. A VCM-based switching method for the most significant bit and reference voltage segments from an insensitive R-string for the last two least significant bits minimize the number of unit capacitors required in the C-R hybrid DAC. The comparator accuracy is improved by an open-loop offset cancellation technique in the first-stage pre-amp. The prototype ADC in a 0.11 μm CMOS process demonstrates the measured differential nonlinearity and integral nonlinearity within 1.18 LSB and 1.42 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 63.9 dB and a maximum spurious-free dynamic range of 77.6 dB at 10 MS/s. The ADC with an active die area of 0.34 mm2 consumes 1.1 mW at 1.0 V and 10 MS/s, corresponding to a figure-of-merit of 87 fJ/conversion-step.

The behavioral model of a split capacitor array involved in the successive approximation register ADC and taking into account the effect of parasitic capacitors

The analysis of the effect of the parasitic capacitors on the split capacitor array digital-to analog converter for use in the successive approximation register analog-to-digital converter is presented. The Verilog-A model of the split capacitor array is developed based on the analysis. The advantages of using this model in the context of the top-down design methodology are considered.

Unit capacitor array based SAR ADC

This paper proposes a new successive approximation register analog-to-digital converter by using a unit capacitor array to implement the digital-to-analog converter. Under the same differential non-linearity specification, the proposed method can consume orders of magnitude less switching power and chip area than all existing solutions, including those using a binary weighted capacitor array (with or without a bridge capacitor) and those using a split capacitor array. The claimed benefits of the proposed method are verified by behavioral simulations.