10-bit Single-Slope ADC with error quantification and double reset technique for CMOS image sensor

Abstract

In this paper, a digital correlated double sampling (CDS)-based 10-bit Single-Slope Analog-to-Digital Converter (SS ADC) with error quantification and double reset technique for CMOS image sensor is proposed. The SS ADC circuit block contains a ramp generator, parallel counters and comparators. The error quantification (EQ) technique is adopted to reduce the clock numbers that are counted in the digital counter and the power consumption during the whole digitizing process. To improve the speed of this SS ADC, the double reset technique is introduced to complete the whole digital CDS (DDS) operation with one ramp, and 256 clocks are saved compared with the conventional one. The Digital-to-Analog Converter (DAC) used in the ramp generator is based on the split-capacitor array with a redundant capacitor, and its linearity performance with capacitor mismatch is analyzed to make the distribution of bits in MSB and LSB arrays. The proposed SS ADC is implemented and simulated through 130 nm process. Under the dark (pixel level is 0.1 V) and bright (pixel level is 1.2 V) condition, the column FPN of 0 LSB and 9.8 LSB are achieved in the readout circuit, and 58.7% and 23.6% of power consumption is saved in the hybrid digital counter, respectively.