No calibration required two-step double-data-rate counter for low-power SS ADC in CMOS image sensors

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This paper presents a low-power two-step double-data-rate (TS-DDR) counter without calibration for column-parallel single-slope analog-to-digital converter (SS ADC) in CMOS image sensor. A resolution alterable TS counting logic, which drives counting circuit to operate as a (N + M)-bit counter for the fine quantization and a M-bit MSB counter for the coarse quantization, is proposed to reduce the dynamic power consumption. As no calibration is required, the proposed counter is compatible with both digital correlated double sampling (D-CDS) and digital correlated multiple sampling (D-CMS). Moreover, a DDR structure without phase matching required for TS counter is employed to further reduce the power consumption. The proposed TS-DDR counter is implemented in 12-bit column-parallel SS ADCs for a CMOS image sensor. As a result, the proposed TS-DDR counter achieves a power consumption saving of at least 55.2% compared to a traditional one. The proposed SS ADC consumes 47.6 μW and has a DNL of +0.45/-0.55 LSB and an INL of +0.73/-2.36 LSB each column at 6.1 μs conversion time.