Abstract
A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.
Highlights
Due to their benefits of low power, low cost and flexible system integration with on-chip circuits, CMOS image sensors (CIS) have been experiencing explosive growth in recent years and have made themselves competitive to charge-coupled devices (CCD), in high-speed videography
This paper proposes a new two-step SS analog-to-digital converter (ADC) using a single ramp voltage and multiple reference voltages
The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate
Summary
Due to their benefits of low power, low cost and flexible system integration with on-chip circuits, CMOS image sensors (CIS) have been experiencing explosive growth in recent years and have made themselves competitive to charge-coupled devices (CCD), in high-speed videography. There exist three analog-to-digital converter (ADC) architectures utilized in CMOS image sensors: the single-channel ADC, the column-parallel ADC and the pixel-level ADC. The column-parallel ADC is the most widely used architecture because it provides a better tradeoff among readout speed, silicon area and power consumption. SAR ADCs have been utilized in high-speed image sensors, but they occupy a large silicon area. Cyclic ADCs occupy less area while providing high speed, but the high-speed operation amplifier (op-amp) in each column consumes more power. SS ADCs have been most widely applied in CMOS image sensors because of their simplicity, low power consumption, high linearity, and small area. They can ensure uniformity between columns and minimize column fixed-pattern noise (FPN). High-speed SS ADCs have been recently reported [5], they use very high clock frequency which in turn leads to high power consumption
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