Spl Sim Research Articles

Study of bending-induced strain effects on MuGFET performance

The impact of stress induced by biaxial mechanical bending on multiple-gate FET (MuGFET) performance is studied. For relatively low levels of bending-induced surface strain (/spl sim/ 0.1%), significant enhancements in the driving current can be achieved and maintained with gate-length scaling. This makes package strain a potentially attractive approach to enhancing MuGFET-based CMOS performance at low cost. For bending-induced strain, the enhancements in electron mobility and [110] hole mobility are well predicted by the piezoresistance model using the coefficients for bulk-Si, but the impact of stress on (100) hole mobility is more complex.

Modeling and measurement of the acoustic lead sensitivity in sagnac fiber sensor arrays

In this study, a theoretical model of the lead (delay coil and array buses) sensitivity in Sagnac sensor arrays (SSA) for underwater acoustic detection, which induces a spurious pickup and thus a sensor error, is described. In the worst-case scenario, the pickup in a 20-km coil is predicted to be reasonable in deep waters (quietest) (about 17 dB higher than the hydrophone signal) but fairly high (/spl sim/ 52 dB) in shallow waters (noisiest). We show that this pickup can be eliminated for the first few hydrophones in the array by optically folding or double winding the coil, although these approaches are not as effective for the most distant hydrophones in long arrays (/spl ges/ 1 km). These figures are confirmed experimentally in an SSA: Folding a 5-km coil decreased the relative pickup from /spl sim/-42 dB for the first hydrophone and by /spl sim/-8 dB for a hydrophone 1 km down the array. These results concur that for most practical arrays, it is imperative to isolate the coil in an acoustically shielded enclosure, which will reduce the coil pickup to an arbitrarily low level for all hydrophones. Theory and experiment also agree that the pickup in the array buses increases in proportion to the distance along the array. In the worst-case scenario (spherical acoustic wave incident normal to the array), the pickup in a 1-km bus is predicted to be /spl sim/-7 dB in quiet waters and /spl sim/-40 dB in noisy waters. However, in the field, the probability of this event is expected to be extremely low, and these values will be typically at least 15 dB weaker. Nevertheless, in long arrays, the bus pickup must be reduced, which can be achieved by desensitizing the bus fiber and/or pickup subtraction. Combined, these two techniques are expected to make the bus pickup under normal conditions negligible in deep-water applications (/spl sim/-48 dB) and acceptable in noisier shallow-water applications (/spl sim/-15 dB).

Diamond FET using high-quality polycrystalline diamond with f/sub T/ of 45 GHz and f/sub max/ of 120 GHz

Using high-quality polycrystalline chemical-vapor-deposited diamond films with large grains (/spl sim/100 μm), field effect transistors (FETs) with gate lengths of 0.1 μm were fabricated. From the RF characteristics, the maximum transition frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and the maximum frequency of oscillation f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> were /spl sim/ 45 and /spl sim/ 120 GHz, respectively. The f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> values are much higher than the highest values for single-crystalline diamond FETs. The dc characteristics of the FET showed a drain-current density I/sub DS/ of 550 mA/mm at gate-source voltage V/sub GS/ of -3.5 V and a maximum transconductance g/sub m/ of 143 mS/mm at drain voltage V/sub DS/ of -8 V. These results indicate that the high-quality polycrystalline diamond film, whose maximum size is 4 in at present, is a most promising substrate for diamond electronic devices.

RF MEMS switch integrated on printed circuit board with metallic membrane first sequence and transferring

This letter reports, for the first time, on RF MEMS switches integrated on flexible printed circuit boards (i.e., FR-4) using transfer technology. The devices were first processed on Si-substrate using a modified MEMS sequence and subsequently transferred onto an FR-4 substrate by thermal compressive bonding, mechanical grinding, and wet removal of silicon. The switches were demonstrated with flat metal membrane (top electrode), precisely controlled gap between the membrane and bottom electrode, low insertion loss (/spl les/ 0.15 dB at 20 GHz), and high isolation (/spl sim/ 21 dB at 20 GHz). This technology shows the potential to monolithically integrate RF MEMS components with other RF devices on organic substrate for RF system implementation.

High-speed and uncooled operation of 1.3-/spl mu/m InGaAsP strain-compensated MQW BH lasers fabricated on patterned InP substrates

The fabrication and characteristics of 1.3-/spl mu/m InGaAsP strain-compensated multiquantum well (SCMQW) buried heterostructure (BH) laser diodes (LDs) grown by selective metal-organic chemical vapor epitaxy on a patterned InP substrate are demonstrated. The photoluminescence (PL) of the SCMQW active region grown on the patterned grooves has a narrow full-width at half-maximum of /spl sim/ 47 meV. The BH LDs exhibit a threshold current of 6.8 mA, a slope efficiency of 0.45 mW/mA, and a light output power exceeding 30 mW at 80 mA and 20/spl deg/C. The maximum operating temperature is 120/spl deg/C with a characteristic temperature of 72 K in 20/spl deg/C-80/spl deg/C. The 3-dB modulation bandwidth can be extended as far as 11.4 GHz under a bias level of 40 mA, and the back-to-back tests show a clear and symmetric eye diagram at 10 Gb/s with a PRBS of 2/sup 31/-1 word length and a peak-to-peak voltage of 1.08 V at 85/spl deg/C. The average increase in operational current is smaller than 0.84% after the 1500-h aging test. The mean time of the BH LDs operated at 85/spl deg/C to fail is calculated as 9/spl times/10/sup 4/ h. These BH LDs satisfy the reliability requirement for strict loop environment and 10-Gb Ethernet application without special hermetic packaging.

Index profile design for high-bandwidth W-shaped plastic optical fiber

Modal dispersion in plastic optical fibers with W-shaped refractive index profiles (W-shaped POFs) is investigated. The authors focus on the effect of the refractive index valley at the boundary of core and cladding on the group delay. In this paper, particularly, the relationship between the depth of the index valley and the modal dispersion is highlighted. In order to analyze the relationship precisely, the authors prepare the W-shaped POFs with a high numerical aperture (NA /spl sim/ 0.25), which are expected to show the effect of W-shaped profile more clearly than the W-shaped POFs with an NA of 0.2. As a result, the modal dispersion is strongly dependent on the depth of the index valley, which means that the control of the index valley is required, in order for minimum modal dispersion. Furthermore, by evaluating the output pulsewidth from the W-shaped POFs, the authors design the optimum index valley for the maximum bandwidth performance.

Investigation of tuning characteristics of electrically tunable long-period gratings with a precise four-Layer model

In this paper, an investigation of the tuning characteristics of electrically tunable long-period gratings (LPGs) is presented. A precise four-layer model is used to quantitatively analyze the tuning potential of the gratings, and experimental data are provided to support the analysis. The four-layer model includes a silica core layer with an inscribed LPG, a thin silica cladding layer (/spl sim/40 /spl mu/m), an ultrathin (/spl sim/ 50 nm) high refractive index indium-tin dioxide (ITO) inner electrode layer, and a tunable electrooptic (E-O) polymer layer. It has been found that the inner electrode layer, made of high refractive index ITO, can be modeled as a high refractive index overlay and causes the forward-propagating modes in the thin silica cladding to reorganize as the ambient refractive index changes. This reorganization effect can lead to a significant increase (ten plus fold) in the tuning range of LPG tunable filters. Moreover, the required specifications of the tunable polymer layer are quantitatively analyzed. Finally, the required characteristics of the E-O polymer is realized by using a nanocomposite ferroelectric relaxor poly(vinylidene fluoride-trifluoroethylene-chlorofluoroethylene) terpolymer.

ScN/sub x/ gate on atomic layer deposited HfO/sub 2/ and effect of high-pressure wet post deposition annealing

For nMOS devices with HfO/sub 2/, a metal gate with a very low workfunction is necessary. In this letter, the effective workfunction (/spl Phi//sub m,eff/) values of ScN/sub x/ gates on both SiO/sub 2/ and atomic layer deposited (ALD) HfO/sub 2/ are evaluated. The ScN/sub x//SiO/sub 2/ samples have a wide range of /spl Phi//sub m,eff/ values from /spl sim/ 3.9 to /spl sim/ 4.7 eV, and nMOS-compatible /spl Phi//sub m,eff/ values can be obtained. However, the ScN/sub x/ gates on conventional post deposition-annealed HfO/sub 2/ show a relatively narrow range of /spl Phi//sub m,eff/ values from /spl sim/ 4.5 to /spl sim/ 4.8 eV, and nMOS-compatible /spl Phi//sub m,eff/ values cannot be obtained due to the Fermi-level pinning (FLP) effect. Using high-pressure wet post deposition annealing, we could dramatically reduce the extrinsic FLP. The /spl Phi//sub m,eff/ value of /spl sim/ 4.2 eV was obtained for the ScN/sub x/ gate on the wet-treated HfO/sub 2/. Therefore, ScN/sub x/ metal gate is a good candidate for nMOS devices with ALD HfO/sub 2/.

Enhancing leakage suppression in carbon-rich silicon junctions

Carbon-incorporated devices exhibit an increase in junction leakage relative to pure Si devices. The authors demonstrate that a leakage suppression of /spl sim/ 50 times can be achieved in carbon-rich (Si:C) junctions. This is accomplished by a prolonged annealing for 1 to 10 min at 850 /spl deg/C (much lower than typical annealing temperature of >1000/spl deg/C) and is attributed to a decrease in interstitial carbon concentration. After a 10-min annealing, the Si:C junctions display a leakage of 4/spl times/10/sup -13/ A//spl mu/m, which is much lower than that of 1050 /spl deg/C spike annealed Si junctions and well within the I/sub off/ requirements of low-standby-power device at the 45-nm node. Carbon-incorporated transistors with a gate length of 0.18 /spl mu/m exhibit an I/sub off/ reduction of /spl sim/ 10 times, compared to pure Si transistors, and both transistors have a similar subthreshold slope of 81 mV/dec.

Laser-assisted processing of VIAs for AlGaN/GaN HEMTs on SiC substrates

Vertical interconnect accesses (VIAs) were fabricated between the source electrode on the front and the ground on the backside of high-power microwave AlGaN/GaN high-electron mobility transistors (HEMTs) on /spl sim/400-μm-thick silicon carbide substrates. Through-wafer microholes with an aspect ratio of up to /spl sim/ 8 were drilled using pulsed UV-laser machining and subsequently metallized using electroplating. The successful implementation of the laser-assisted VIA technology into device processing was proven by dc and RF characterization. When biased at 26 V, a saturated output power of 41.6 W with an associated power-added efficiency of 55% at 2 GHz was achieved for a 20-mm AlGaN/GaN HEMT with through-wafer VIAs.

Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels

The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is /spl sim/ 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.

Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

A study on using a novel metal gate-the Ni fully GermanoSilicide (FUGESI)-in pMOSFETs is presented. Using HfSiON high-/spl kappa/ gate dielectrics and comparing to Ni fully Silicide (FUSI) devices, this paper demonstrates that the addition of Ge in poly-Si gate (with Ge/(Si+Ge)/spl sim/50%) results in: 1) an increase of the effective work function by /spl sim/ 210 mV due to Fermi-level unpinning effect; 2) an improved channel interface; 3) a reduced gate leakage; and 4) the superior negative bias temperature instability characteristics. Low-frequency noise measurement reveals a decreased 1/f and generation-recombination noise in FUGESI devices compared to FUSI devices, which is attributed to the reduced oxygen vacancies (V/sub o/)-related defects in the HfSiON dielectrics in FUGESI devices. The reduced V/sub o/-related defects stemming from Ge at FUGESI /HfSiON interface are correlated with the Fermi-level unpinning effect and the improved electrical characteristics observed in FUGESI devices.

Charge-transport characteristics in bistable resistive Poly(N-vinylcarbazole) films

Charge-transport characteristics of bistable resistive poly(N-vinylcarbazole) films as a function of temperature have been investigated. It is found that the on-state charge transport is dominated by ohmic conduction, hopping with an energy scale of the order of /spl sim/ 20 meV. The off-state charge transport appears to follow a transition from ohmic to space charge limited conduction with a shallow-trap distribution. Nonetheless, the poly(N-vinylcarbazole) (PVK) film does not possess its memory characteristics when operated at temperatures higher than 410 K. The PVK film can be operated at low voltage (< 2 V) with a high on/off current ratio as large as 10/sup 6/.

Real time digital signal processing implementation for an APD-based PET scanner with phoswich detectors

Recent progress in advanced digital signal processing provides an opportunity to expand the computation power required for real time extraction of event characteristics in avalanche photodiode (APD)-based Positron Emission Tomography (PET) scanners. These developments are made possible by a highly parallel data acquisition (DAQ) system based on an integrated analog front-end and a high-speed fully digital signal processing section that directly samples the output of each preamplifier with a free-running, off-the-shelf, 45-MHz analog-to-digital converter that feeds the sampled data into a field programmable gate array (FPGA) VirtexII PRO from Xilinx. This FPGA features /spl sim/ 31 000 logic cells and two PowerPC processors, which allows up to 64 channels to be processed simultaneously. Each channel has its own digital signal processing chain including a trigger, a baseline restorer and a timestamp algorithm. Various timestamp algorithms have been tested so far, achieving a coincidence timing resolution of 3.2-ns full-width at half-maximum (FWHM) for APD coupled to Lutetium Oxyorthosilicate (APD-LSO) and 11.4-ns FWHM for APD coupled to Bismuth Germanium Oxide (APD-BGO) detectors, respectively. Channels are then multiplexed into a DSP processor from Texas Instruments for crystal identification by an ARMAX recursive algorithm borrowed from identification and vector quantization theory. The system can sustain an event rate of 10 000 events/s/channel without electronic dead time.

Spectroscopic Performance of Thick HgI2 Detectors.

This paper presents the spectroscopic performance of two newly developed pixelated HgI2 detectors. These detectors are 1 × 1 × 0.814 cm3 and 1 × 1 × 1.016 cm3 in size. Each detector has four closely packed 1 × mm2 anode pixels at the center of one of the 1 × 1 cm2 surfaces. These anode pixels are surrounded by a large anode. All results presented here are based on events from a sub-volume underneath the anode pixels. In these detectors, signals were read out by a discrete electronics based on multiple A-250 pre-amplifiers and a digital oscilloscope for sampling pulse waveforms. Depth sensing technique was used to correct the depth-dependent variation in photopeak amplitude. Main results presented are: (1) energy resolutions of 0.85 ~ 1.3% have been achieved on these detectors; (2) the electron mobility-lifetime product was measured to be ~1 × 10-2 cm2/V and the measured electron lifetime was ~200 μs and (3) variation in electron drifting properties under different anode pixels were observed. Significant non-uniformity in internal electric field strength was also experimentally demonstrated.

On-chip high speed localized cooling using superlattice microrefrigerators

In this paper, we addressed heating problems in integrated circuits (ICs) and proposed a thin-film thermionic cooling solution using Si/SiGe superlattice microrefrigerators. We compared our technology with the current most common solution, thermoelectric coolers, by strengthening the advantages of its compatible fabrication process as ICs for easy integration, small footprint in the order of /spl sim/ 100/spl times/100 /spl mu/m/sup 2/, high cooling power density, 600W/cm/sup 2/ and fast transient response less than 40 /spl mu/s. The thermoreflectance imaging also demonstrated its localized cooling. All these features combined together to make these microrefrigerators a very promising application for on-chip temperature control, removing hot spots inside IC.

Comprehensive Above-Threshold Analysis of Antiresonant Reflecting Optical Waveguide Edge-Emitting Diode Laser

A three-dimensional (3-D) above-threshold analysis has been performed for laterally antiguided laser structures of the antiresonant-reflecting-optical-waveguide type, of relatively large core width (/spl sim/ 10 /spl mu/m), for high-power, single-spatial-mode operation. A 3-D numerical code has been developed, which takes into account carrier diffusion in the quantum well as well as edge radiation losses. The laser characteristics are calculated as functions of the above-threshold drive level. Within the simulation, 3-5 higher order optical modes on a "frozen background" are computed by the Arnoldi algorithm. Because of the nonuniform gain saturation of the lasing mode, the modal gains for higher order modes increase with the drive current due to increasing overlap of their fields with the two-dimensional gain distribution. The onset of threshold for higher order modes puts an upper limit on the range for stable single-mode operation. The above-threshold analysis is done for various values of the width of the reflector region, below and above the lateral-antiresonance condition. It is found that the maximum intermodal discrimination, which in turn provides the maximum single-mode power, is obtained when the reflector-region width is /spl sim/25 % larger that its value at antiresonance. Then, for 10-/spl mu/m-core devices, stable, single-mode operation is found to occur to drive levels as high as 41 /spl times/ threshold, with single-mode output powers as high as 1.45 W.

A dual-strained CMOS structure through simultaneous formation of relaxed and compressive strained-SiGe-on-insulator

This letter reports on an integration of dual-strained surface-channel CMOS structure, i.e., tensile-strained Si n-MOSFET and compressive strained-SiGe p-MOSFET. This has been accomplished by forming the relaxed and compressive strained-SiGe layers simultaneously on an Si/SiGe-on-insulator (SOI) substrate, through varying SiGe film thicknesses, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state). A thin Si film was selectively deposited over the relaxed SiGe region. The p-MOSFET in compressive (/spl epsiv//spl sim/ -1.07%) strained- Si/sub 0.55/Ge/sub 0.45/ and the n-MOSFET in tensile-strained Si over the relaxed Si/sub 0.80/Ge/sub 0.20/ exhibited significant hole (enhancement factor /spl sim/ 1.9) and electron (enhancement factor /spl sim/ 1.6) mobility enhancements over the Si reference.

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> . High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA/μm were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks

Building on a previously presented compact gate capacitance (C/sub g/-V/sub g/) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I/sub g/-V/sub g/) is provided for both ultrathin SiO/sub 2/ and high-dielectric constant (high-/spl kappa/) gate stacks of equivalent oxide thickness (EOT) down to /spl sim/ 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact C/sub g/-V/sub g/ model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schro/spl uml/dinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO/sub 2/ and high-/spl kappa//SiO/sub 2/ gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO/sub 2/, Si/sub 3/N/sub 4/, and high-/spl kappa/ (e.g., HfO/sub 2/) gate stacks on (100) Si with EOTs down to /spl sim/ 1-nm show excellent agreement.