Enhancing leakage suppression in carbon-rich silicon junctions

Abstract

Carbon-incorporated devices exhibit an increase in junction leakage relative to pure Si devices. The authors demonstrate that a leakage suppression of /spl sim/ 50 times can be achieved in carbon-rich (Si:C) junctions. This is accomplished by a prolonged annealing for 1 to 10 min at 850 /spl deg/C (much lower than typical annealing temperature of >1000/spl deg/C) and is attributed to a decrease in interstitial carbon concentration. After a 10-min annealing, the Si:C junctions display a leakage of 4/spl times/10/sup -13/ A//spl mu/m, which is much lower than that of 1050 /spl deg/C spike annealed Si junctions and well within the I/sub off/ requirements of low-standby-power device at the 45-nm node. Carbon-incorporated transistors with a gate length of 0.18 /spl mu/m exhibit an I/sub off/ reduction of /spl sim/ 10 times, compared to pure Si transistors, and both transistors have a similar subthreshold slope of 81 mV/dec.