A dual-strained CMOS structure through simultaneous formation of relaxed and compressive strained-SiGe-on-insulator

Abstract

This letter reports on an integration of dual-strained surface-channel CMOS structure, i.e., tensile-strained Si n-MOSFET and compressive strained-SiGe p-MOSFET. This has been accomplished by forming the relaxed and compressive strained-SiGe layers simultaneously on an Si/SiGe-on-insulator (SOI) substrate, through varying SiGe film thicknesses, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state). A thin Si film was selectively deposited over the relaxed SiGe region. The p-MOSFET in compressive (/spl epsiv//spl sim/ -1.07%) strained- Si/sub 0.55/Ge/sub 0.45/ and the n-MOSFET in tensile-strained Si over the relaxed Si/sub 0.80/Ge/sub 0.20/ exhibited significant hole (enhancement factor /spl sim/ 1.9) and electron (enhancement factor /spl sim/ 1.6) mobility enhancements over the Si reference.