Spin-transfer Torque Random Access Memory Cells Research Articles

EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit

Spin Transfer Torque Random Access Memory (STT-RAM) has garnered interest due to its various characteristics such as non-volatility, low leakage power, high density. Its magnetic properties have a vital role in STT switching operations through thermal effectiveness. A key challenge for STT-RAM in industrial adaption is the high write energy and latency. In this paper, we overcome this challenge by exploiting the stochastic switching of STT-RAM cells and, in tandem, with circuit-level approximation. We enforce the robustness of our technique by analyzing the vulnerability of write operation against radiation-induced soft errors and applying a low-cost improvement. Due to serious reliability challenges in nanometer-scale technology, the robustness of the proposed circuit is also analyzed in the presence of CMOS and magnetic tunnel junction (MTJ) process variation. Compared to the state-of-the-art, we achieve 33.04% and 5.47% lower STT-RAM write energy and latency, respectively, with a 3.7% area overhead, for memory-centric applications.

Optoelectronic Readout of STT-RAM Based on Plasmon Drag Effect

An opto-electronic readout of the memory state in spin transfer torque random access memory (STT-RAM) cells is proposed. A single optical beam illuminating an array of STT-RAM cells creates electrical potential along each STT-RAM cell due to optical rectification that can be further enhanced through plasmon drag effect (PLDE). Then, the photo-induced voltage is assumed to be measured by conventional electronics. Here, a theoretical modeling is performed, where the results provide an estimate of the photo-induced voltage in each memory cell and its variation with respect to the changes in state of the memory cell (parallel vs anti-parallel). Our study shows that the plasmonic enhancement facilitates ${\sim }$ 20 times enhancement in the voltage change due to state change of the each memory cell, compared to the case of out-of-resonance excitation. This enhancement potentially improves the memory readout rate if a proper supporting electronic circuit is available.

FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design

Modern graphics processing units (GPUs) exhibit increasing demands for register files (RFs) with larger capacity and bank sizes, which jeopardize the traditional SRAM-based RF designs due to their large die area and long access latency. Recent hybrid RF designs, e.g., SRAM and spin-transfer torque random access memory (STT-RAM)-based RFs, mitigate the issue by exploiting the density and performance advantages in STT-RAM and SRAM, respectively. However, existing hybrid RF designs adopt coarse integration that has limited write bandwidth between SRAM and STT-RAM, which restricts the adoption of different warp schedulers at runtime. In this article, we propose FRF, a warp-scheduler friendly fine-grained hybrid RF design using SRAM/STT-RAM hybrid cell (HC) structures. By integrating one SRAM cell and $N$ STT-RAM cells as one HC, FRF exploits internal write paths to enlarge the access bandwidth between SRAM and STT-RAM and thus greatly optimizes the area and performance. FRF enables the concurrent context-switching such that different warp schedulers may be adopted at runtime. FRF adopts interleaved register mapping (IRM) and on-demand register remapping to further improve the utilization of SRAM in each HC. Our experimental results show that, on average, FRF achieves 50% performance improvement and 40% energy consumption reduction over the coarse-grained hybrid design when adopting loose round-robin (LRR), and achieves 159% efficiency improvement over pure STT-RAM-based RF.

A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs

A combination of semiconductor integrated circuits (IC) and a dense array of scaled magnetic tunnel junctions (MTJ) makes promising Spin-Transfer Torque Random Access Memory (STT-RAM). This emerging memory minimizes the leakage power consumption and provides a high density at scaled technologies. In this paper, we propose a novel non-destructive self-reference sensing scheme for STT-RAM. The proposed technique overcomes the large bit-to-bit variation of MTJ resistance. In the proposed scheme, the stored value in the STT-RAM cell preserves, hence, the long write-back operation is eliminated. Besides, the sensing scheme is accomplished in one step. In this scheme, the Bit-Line is pre-charged and then discharged during read operation. The MTJ resistance state can be found by comparing the time constant of discharging. The simulation results show the overall sensing time is 4 ns when the Bit-Line capacitance is equal to 200 fF.

Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications

Spintronic memories are one of the most promising candidates as a universal memory. Although they offer superior energy efficiency over the conventional memories, benefiting from approximate computing approach, some novel techniques can be applied to lower the power consumption even further. In this brief, we propose a progressive scaling scheme for spin-transfer torque random access memory (STT-RAM) arrays, by which the power consumption is reduced at the expense of small quality degradation. According to the proposed approach, access transistors in STT-RAM cells are scaled based on an optimized scaling factor, where least significant bits and most significant bits come with different bit error rates in the data word. Simulation results show that the proposed approach provides 36.7% write power dissipation and 25% die area savings, respectively, while negligible quality degradation is observed based on mean structural similarity index.

Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design

Rapidly increasing demands for memory capacity and severe technical scaling challenges of conventional memory technologies motivated recent investments on next-generation nonvolatile memory technologies. As a promising candidate, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive properties, such as nanosecond access time, high integration density, nonvolatility, and excellent CMOS integration compatibility. However, similar to all other nano-devices, the performance and reliability of STT-RAM cells are greatly affected by process variations, device operating uncertainties, and environmental fluctuations. As a result, the read and write operations of STT-RAM demonstrate some variabilities and errors. In this paper, we systematically analyze the impacts of CMOS and magnetic tunneling junction (MTJ) process variations, MTJ resistance switching randomness that are induced by intrinsic thermal fluctuations, and working temperature changes on STT-RAM cell designs. The STT-RAM cell reliability issues in both read and write operations are first investigated. A combined circuit and magnetic simulation platform is then established to quantitatively study the persistent and nonpersistent errors in STT-RAM cell operations. Our analysis proved the importance of a full statistical design method in STT-RAM designs for design pessimism minimization.

Micro‐architectural approach to the efficient employment of STTRAM cells in a microprocessor register file

In this paper, the authors propose two approaches that employ spin transfer torque random access memory (STTRAM) in the design of the register file, an important part of embedded processors. However, STTRAM suffers from both endurance and latency in the write operation. Consequently, employing STTRAM in the register file entails two challenges: (i) the lifetime significantly decreases as data are frequently written into a register file; (ii) the delay of the critical path increases as a result of the slow write operation. They have proposed using two well-known micro-architectural approaches: the last-write-update (LWU) and the value locality (VL), to minimize the number of write operations into a register. The main observation behind LWU is that only the last write operations of certain registers in the re-order buffer should be considered. VL exploits the fact that a limited number of values are more likely to be written into a register file. Their simulation shows that by employing the LWU and VL approaches, the lifetime of the STTRAM-based register file, compared with the lifetime of traditional static RAM-based register file architecture, extends to about 40 years on average and around 3.5 years in the worst case while improving power consumption by 30%.

Dual Referenced Composite Free Layer Design for Improved Switching Efficiency of Spin-Transfer Torque Random Access Memory

A composite free layer spin-transfer torque random access memory (STT-RAM) cell is proposed for ultra-high density memory. The structure consists of three layers-a high anisotropy interior layer and two low anisotropy outer layers that assist the switching of the interior layer via exchange coupling. Efficiencies (kBT/μA) of 4.5 and 4.1 are achieved for the proposed structure with perpendicular and longitudinal anisotropies, respectively. An efficiency of 4.3 is obtained for the state-of-the-art single-layer dual-referenced structure with perpendicular anisotropy. Simulation of the conventional singlelayer structure with perpendicular anisotropy yields an efficiency of 1.6. Therefore, the proposed structure with perpendicular anisotropy achieves an improvement of 5% and 181% relative to the state-of-the-art dual-referenced and conventional STT-RAM cells, respectively. Furthermore, use of low anisotropy assistive layers enables reduction of Gilbert damping and an increase of partial spin polarization within those low anisotropy layers-not feasible with single layer structures that require high anisotropy for thermal stability. This significantly increases perpendicular and longitudinal efficiencies to 8.5 and 6.8, respectively. Therefore, this augmented proposed structure with perpendicular anisotropy achieves an improvement of 99% and 446% relative to the state-of-the-art dual-referenced and conventional STT-RAM cells, respectively.

Graphene-Based STT-RAM Cell With Improved Switching for Scaled Technology Nodes

Spin-transfer torque random-access memory (STT-RAM) is a nonvolatile, scalable, and fast memory structure, which benefits from high endurance and relatively low power consumption. However, there are some challenges in designing STT-RAM such as the tradeoff between decreasing the write current and the retention time. Increasing the write voltage as the cell size is scaled down is another challenge for STT-RAM due to the increasing resistance of its magnetic tunnel junction (MTJ). In this paper, a novel STT-RAM cell structure with a graphene-based spin filter including three graphene layers as MTJ is proposed for sub-20 nm technology nodes (e.g., 14 nm and beyond). By flowing a small (e.g., $3~\mu \text{A}$ ) and short width current pulse (e.g., 1 ns) through the center graphene layer, a reduction of 69% in the amplitude of the intrinsic switching current density (38% less than the predicted value for the conventional in-plane STT-RAM) is achieved without any penalty of data retention time for an 8 nm technology node. Furthermore, by flowing current through the center graphene layer, the intrinsic switching voltage of the proposed structure is decreased by 27%, 51%, and 59% for 14, 10, and 8 nm widths of the MTJ, respectively. The behavior of the proposed structure in a fast (precessional) switching mode (switching time less than 3 ns) is evaluated. Consequently, a reduction of 38% in the switching current density and the switching voltage can be attained for the 8 nm technology node, using the proposed idea. Simulation results are obtained using an object-oriented micromagnetic framework.

Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach

Spin-transfer torque random access memory (STT-RAM) is a promising candidate for universal memory due to its speed, scalability, and non-volatility. A wide range of write speeds from <inline-formula><tex-math>$1$</tex-math></inline-formula> to <inline-formula><tex-math>$100\,\mathrm {ns}$</tex-math></inline-formula> have been reported for STT-RAM. As the storage element of an STT-RAM cell, the switching current of magnetic tunnel junction (MTJ) is inversely proportional to the write pulse width. In this work, we propose a methodology to design STT-RAM for different optimization goals such as read performance, write performance, and write energy by leveraging the trade-off between write current and write time of MTJ. To enable STT-RAM design in advanced technology nodes beyond 22 nm, we model perpendicular MTJ (PMTJ) as the storage element and FinFET as the access transistor. Our study shows that reducing write pulse width will harm read latency and energy. It is observed that “sweet spots” of write pulse width which minimize the write energy or write latency of an STT-RAM macro may exist. The optimal write pulse width depends on both the device and the architecture specifications. The impact of process variations including the MTJ and the FinFET access transistor are also analyzed.

A graphite based STT-RAM cell with reduction in switching current

Spin Transfer Torque Random Access Memory (STT-RAM) is a serious candidate for “universal memory” because of its non-volatility, fast access time, high density, good scalability, high endurance and relatively low power dissipation. However, problems with low write speed and large write current are important existing challenges in STT-RAM design and there is a tradeoff between them and data retention time. In this study, a novel STT-RAM cell structure which uses perfect graphite based Magnetic Tunnel Junction (MTJ) is proposed. First, the cross-section of the structure is selected to be an ellipse of 45nm and 180nm dimensions and a six-layer graphite is used as tunnel barrier. By passing a lateral current with a short pulse width (before applying STT current and independent of it) through four middle graphene layers of the tunnel barrier, a 27% reduction in the amplitude of the switching current (for fast switching time of 2ns) or a 58% reduction in its pulse width is achieved without any reduction in data retention time. Finally, the effect of downscaling of technology on the proposed structure is evaluated. A reduction of 31.6% and 9% in switching current is achieved for 90 and 22nm cell width respectively by passing sufficient current (100µA with 0.1ns pulse width) through the tunnel barrier. Simulations are done using Object Oriented Micro Magnetic Framework (OOMMF).

STT-RAM Cache Hierarchy With Multiretention MTJ Designs

Spin-transfer torque random access memory (STT-RAM) is the most promising candidate to be universal memory due to its good scalability, zero standby power, and radiation hardness. Having a cell area only 1/9 to 1/3 that of SRAM, allows for a much larger cache with the same die footprint. Such reduction of cell size can significantly shrink the cache array size, leading to significant improvement of overall system performance and power consumption, especially in this multicore era where locality is crucial. However, deploying STT-RAM technology in L1 caches is challenging because write operations on STT-RAM are slow and power-consuming. In this paper, we propose a range of cache hierarchy designs implemented entirely using STT-RAM that deliver optimal power saving and performance. In particular, our designs use STT-RAM cells with various data retention times and write performances, made possible by novel magnetic tunneling junction designs. For L1 caches where speed is of utmost importance, we propose a scheme that uses fast STT-RAM cells with reduced data retention time coupled with a dynamic refresh scheme. In the dynamic refresh scheme, another emerging technology, memristor, is used as the counter to monitor the data retention of the low-retention STT-RAM, achieving a higher array area efficiency than an SRAM-based counter. For lower level caches with relatively larger cache capacities, we propose a design that has partitions of different retention characteristics, and a data migration scheme that moves data between these partitions. The experiments show that on the average, our proposed multiretention level STT-RAM cache reduces total energy by as much as 30%–74.2% compared to previous single retention level STT-RAM caches, while improving instruction per cycle performance for both two-level and three-level cache hierarchies.

STT-RAM CELL DESIGN CONSIDERING MTJ ASYMMETRIC SWITCHING

As one promising candidate for next-generation nonvolatile memory technologies, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive features, such as nanosecond access time, high integration density, nonvolatility, and good CMOS process compatibility. In this paper, we address the asymmetry in the write operations of STT-RAM cells: the mean and the deviation of the write latency for the switching from low- to high-resistance state is much longer or larger than that of the opposite direction. Some special design concerns, e.g., the data-dependent write reliability, are raised by this observation. We systematically analyze the root reasons for the asymmetric switching of MTJs, including the thermal-induced statistical MTJ magnetization process, the asymmetric biasing condition of NMOS transistors, and the device variations of both NMOS and MTJ. Their impacts on STT-RAM write operations were also investigated. At last, we explore the design spaces of different STT-RAM cell structures by considering the asymmetry of write operations.

STT-RAM Cell Optimization Considering MTJ and CMOS Variations

Spin-transfer torque random access memory (STT-RAM) becomes a promising technology for future computing systems for its fast access time, high density, nonvolatility, and small write current. However, like all the other nanotechnologies, STT-RAM suffers from process variations and environment fluctuations, which significantly affect the performance and stability of magnetic tunneling junction (MTJ) devices. In this study, we combine magnetic and circuit simulations to quantitatively analyze the impacts of MTJ and CMOS variations on the STT-RAM designs. Both bit-to-bit and cycle-by-cycle variations are considered. A robust STT-RAM design flow is also proposed.

Performance, Power, and Reliability Tradeoffs of STT-RAM Cell Subject to Architecture-Level Requirement

Large switching current and long switching time have significantly limited the adoption of spin-transfer torque random access memory (STT-RAM). Technology scaling, moreover, makes it very challenging to reduce the switching current while maintaining the reliability of magnetic tunneling junction (MTJ) to be similar to that of the earlier generations. In this work, we shall exploit a key insight that in the most on-chip caches where STT-RAM is most likely to be deployed, the lifespan of the data stored in the memory cells is much shorter than the data retention time requirement assumed in STT-RAM development, namely, 4~10 years. We also quantitatively investigated the possibility of trading off MTJ nonvolatility for improved switching performance, e.g., the switching time and/or current, under architectural level guidance. We further proposed and evaluated a hybrid memory design technique that partitions the on-chip STT-RAM cache into two parts with different nonvolatility performances so as to better fit the diverse retention time requirements of different data sets.

Simulation study of new 3-terminal devices for high speed STT-RAM

To improve the performance of spin transfer torque random access memory (STT-RAM), especially writing speed, we propose three modified 3-terminal STT-RAM cells. A magnetic dynamic process in the new structures was investigated through micro-magnetic simulation. The best switching speed of the new structures is 120% faster than that of the rectangular 3-terminal device. The optimized 3-terminal device offers high speed while maintaining the high reliability of the 3-terminal structure.

Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies

We propose a magnetic and electric level spin-transfer torque random access memory (STT-RAM) cell model to simulate the write operation of an STT-RAM. The model of a magnetic tunneling junction (MTJ) is modified to take into account the electrical response of the MOS transistor that is connected to the MTJ. A dynamic design flow is also proposed to minimize any unnecessary design margin in an STT-RAM cell design by leveraging from the new STT-RAM cell model. The design of an STT-RAM cell with a one-transistor-one-MTJ (1T1J) structure shows that our technique can reduce more than 22% of the STT-RAM cell area, compared with a conventional STT-RAM cell model at a TSMC 90-nm technology node. The performance and the reliability of the memory cell were unaffected. By using our model, we analyzed the scalability of STT-RAM technology down to a 22-nm Bulk-CMOS technology node. The tradeoffs among the MTJ switching current, the thermal stability of the MTJ and the MOS transistor driving strength are discussed. Some magnetic- and circuit-level solutions to achieve 9F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> STT-RAM cell area at 22-nm technology node are also discussed.