Spin-transfer Torque RAM Research Articles

Sports Smart Data Writing Based on New-Type Semiconductor Nonvolatile Storage Mode

The development of smart sports has just taken a new chapter. Based on the digital transformation in all aspects today, the data content of smart sports with a large number of branches is huge. However, the current storage system, an external storage disk, has not adapted to the computer’s increasingly high requirements for IO performance; DRAM- and SRAM-based memory and cache also face power consumption and capacity expansion problems; the storage system on the overall performance of the computer system constraints is increasingly prominent. Based on the data storage of smart sports for digital transformation, this article proposes a smart for the writing of sports data; a better cache method has been explored under the new semiconductor nonvolatile cache mode. The experimental results in this article show that by comparing single-value and dual-value STT-RAM (spin-torque transfer RAM) caches, the three-valued cache with hierarchical mapping of page swap design has a significant improvement in IPC performance under each test load, compared with single-value STT-RAM caches. Compared with the value type, the average performance has increased by 16%; the overall energy consumption including memory has been reduced by an average of 12.3%.

Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads

Wearable devices have grown exponentially in popularity in both consumer and industrial applications in recent years. Despite their stringent area and energy constraints, these devices are processing increasingly complex and data-rich workloads, necessitating innovative area- and energy-efficient computing solutions and architectures. This paper explores spin-transfer torque RAM (STT-RAM) as a candidate for designing area- and energy-efficient wearable processor caches. First, we analyze the memory footprints of 16 real-world wearable workloads and compare them to general-purpose benchmarks like SPEC 2017 and MiBench. Then, we analyze the wearable workloads’ memory characteristics to reveal that wearable workloads are highly read-intensive, making them less vulnerable than general-purpose workloads to the write latency/energy overheads inherent in STT-RAM caches. Our analysis also reveals that wearable workloads have low cache variability needs, and their cache blocks exhibit short and stable lifetimes. Against the background of this analysis, we explore the tradeoffs of STT-RAM cache architecture designs for the wearable workloads. Specifically, we explore a simple adaptable design that aims to optimize latency or energy, based on runtime needs, without introducing significant design or area overhead. Our analysis shows that STT-RAM caches offer much promise for energy- and area-efficient wearable computing, without introducing much performance overheads.

CORIDOR: Using CO herence and Tempo R al Local I ty to Mitigate Read D isurbance Err OR in STT-RAM Caches

In the deep sub-micron region, “spin-transfer torque RAM” (STT-RAM ) suffers from “read-disturbance error” (RDE) , whereby a read operation disturbs the stored data. Mitigation of RDE requires restore operations, which imposes latency and energy penalties. Hence, RDE presents a crucial threat to the scaling of STT-RAM. In this paper, we offer three techniques to reduce the restore overhead. First, we avoid the restore operations for those reads, where the block will get updated at a higher level cache in the near future. Second, we identify read-intensive blocks using a lightweight mechanism and then migrate these blocks to a small SRAM buffer. On a future read to these blocks, the restore operation is avoided. Third, for data blocks having zero value, a write operation is avoided, and only a flag is set. Based on this flag, both read and restore operations to this block are avoided. We combine these three techniques to design our final policy, named CORIDOR. Compared to a baseline policy, which performs restore operation after each read, CORIDOR achieves a 31.6% reduction in total energy and brings the relative CPI (cycle-per-instruction) to 0.64×. By contrast, an ideal RDE-free STT-RAM saves 42.7% energy and brings the relative CPI to 0.62×. Thus, our CORIDOR policy achieves nearly the same performance as an ideal RDE-free STT-RAM cache. Also, it reaches three-fourths of the energy-saving achieved by the ideal RDE-free cache. We also compare CORIDOR with four previous techniques and show that CORIDOR provides higher restore energy savings than these techniques.

Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories

Emerging Non-Volatile Memories (NVMs) such as Magnetic RAM (MRAM), Spin-Transfer Torque RAM (STTRAM), Phase Change Memory (PCM) and Resistive RAM (RRAM) are very promising due to their low (static) power operation, high scalability and high performance. However, these memories bring new threats to data security. In this paper, we investigate their vulnerability against Side Channel Attack (SCA). We assume that the adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. First, we show our analysis of simulation results. Then, we use commercial NVM chips to validate the analysis. We also investigate the effectiveness of encoding against SCA on emerging NVMs. Finally, we summarize two new flavors of NVMs that can be resilient against SCA. To the best of our knowledge, this is the first attempt to do a comprehensive study of SCA vulnerability of the majority of emerging NVM-based cache.

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.

SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM

Emerging nonvolatile memories (NVMs), such as resistive RAM (RRAM) and spin-transfer-torque RAM (STTRAM), present exciting opportunities for data storage applications and offer improved access speeds, retention times, power consumption, and scalability. However, these technologies leak the Hamming weight of data through power side-channel during read and write operations. We propose a technique leveraging on-chip capacitor and voltage regulator (VR) that powers the NVM read/write operations. The side-channel leakage is eliminated due to the isolation of memory array from the external power supply during read/write operations. The residual charge on capacitor bank is discarded safely to prevent information leakage during capacitor recharging. The VR ensures a steady voltage during the entire read/write operations even though the capacitor discharges. The design presents a performance (instructions per cycle) degradation of 0.53%-1.2% under parsec and splash-2 benchmarks and incurs an area overhead of ~ 3.54×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> % and an energy overhead of ~ 3.05 ×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> % for a 4-Mb RRAM memory array. For a 64-bit word, the design improves security by 2.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> × to 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">64</sup> ×. SecNVM should be used in small security-critical memory macros to limit the overhead. SecNVM is generic and could protect any security module such as encryption engines, against power side-channel attacks.

A cache consolidation design of MLC STT-RAM for energy efficiency enhancement on cyber-physical systems

Owing to the energy-constraint nature of cyber-physical systems (CPS), energy efficiency has become a primary design consideration for CPS. On CPS, owing to the high leakage power issue of SRAM, the major portion of its energy consumption comes from static random-access memory (SRAM)-based processors. Recently, with the emerging and rapidly evolving nonvolatile Spin-Transfer Torque RAM (STT-RAM), STT-RAM is expected to replace SRAM within processors for enhancing the energy efficiency with its near-zero leakage power features. The advances in Magnetic Tunneling Junction (MTJ) technology also realize the multi-level cell (MLC) STT-RAM to pack more cells with the same die area for achieving the memory density. However, the write disturbance issue of MLC STT-RAM prevents STT-RAM from properly resolving the energy efficiency of CPS. Although studies have been proposed to alleviate this issue, previous strategies could induce additional management overhead due to the use of counters or lead to frequent swap operations. Such an observation motivates us to propose an effective and simple strategy to combine direct and split cache mapping designs to enhance the energy efficiency of MLC STT-RAM. A series of experiments have been conducted on an open-source emulator with encouraging results.

Computational Failure Analysis of Resistive RAM Used as a Synapse in a Convolutional Neural Network for Image Classification

Abstract Various NVM technologies are being explored for neuromorphic system realization, including resistive RAM, ferroelectric RAM, phase change RAM, spin transfer torque RAM, and NAND flash. This article discusses the potential of RRAM for such applications and evaluates key performance and reliability metrics in the context of neural network image classification. The authors conclude that the accuracy-power tradeoff may be further improved using alternative material stacks and multi-layer dielectrics so as to achieve better control of the oxygen vacancy or metallic filamentation process that governs RRAM switching characteristics.

Exploring Applications of STT-RAM in GPU Architectures

Use of modern GPUs has been extended from traditional 3D graphic processing to computing acceleration of many scientific, engineering, and enterprise applications. In modern GPUs, on-chip memory capacity keeps increasing to support thousands of chip-resident threads. For example, a large register file is needed in order to efficiently process highly-parallel threads in single instruction multiple thread (SIMT) fashion, and a large shared memory is often implemented to allow data sharing among the threads on the chip. On-chip memory capacity of GPUs, however, is highly constrained by large memory cell area and high static power consumption of conventional SRAM implementation. In this work, we propose to utilize the emerging multi-level cell (MLC) spin-transfer torque RAM (STT-RAM) technology to implement register file and shared memory in GPUs. Compared to SRAM, MLC STT-RAM (or MLC-STT) has a much smaller cell area as well as ultra-low standby power, thanks to the non-volatility of MLC-STT technology. Hence, the footprint and leakage power of the implemented memory components are substantially reduced. Moreover, in light of asymmetric performance of soft and hard bits of a MLC-STT cell, we propose a dynamic data remapping strategy in register file and shared memory implementations that allows a flexible tradeoff between the memory access time and the available capacity: frequently-accessed data is always mapped to the fast rows built with the soft bits of the MLC-STT cells while the slow rows composed of the hard bits are used only when a larger capacity is critically needed. We also develop a novel rescheduling scheme to minimize the waiting time of the issued warps to access register banks in the register file, which is induced by the long writeback operations through the reordering of the issued warps. Finally, an early termination technology is also applied to save the write energy of the shared memory if the bits of the memory do not flip. Experimental results on benchmarks of ISPASS2009, Rodinia, Parboil, and CUDA show that on average, MLC-STT register file can achieve 3.28% system performance improvement, 9.48% energy reduction, and 38.9% energy efficiency improvement compared to conventional SRAM-based design. Meanwhile, MLC-STT shared memory leads to 3.45% system performance improvement, 49.3% energy reduction, and 116% energy efficiency improvement.

Spintronics - A Dive Into the Future

We already know that electrons have a charge along with a spin, but until recently, these two have been considered separately. The motion of electric charge is considered as the heart of electronic circuits, and the flow of electron spin plays a crucial role in spintronic circuits. Adding the spin degree of freedom provides new capabilities, new effects, and new functionalities. It all started with the discovery of the Giant Magnetoresistance (GMR) in 1988, which opened the road to an effective control of the motion of the electron charges by focusing on their spin through the orientation of magnetization. Today, spintronics has entered into almost every household as the read sensors for the hard drives present in every desktop and most laptops. Magnetic Random Access Memory (MRAM) and Spin Transfer Torque (STT) RAM are replacing Static RAM where ultra-dense memories are not required. Soon these spintronic memories will penetrate the cell phone market because they offer lower power and are non-volatile. The potential held by Spintronics is very promising for new advancements in science and technology in the 21st century. This paper discusses the evolution of spintronics from the initial research of spin-dependent transport in ferromagnetic materials to the discovery of the giant magnetoresistance and to the most recent advances. Today, this field of research is extending considerably, with very encouraging new technologies like the phenomena of spin transfer, molecular spintronics, nanoscale spintronics, and single-electron spintronics.

TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache

Spin-transfer torque RAM (STT-RAM) is an emerging non-volatile memory that has been recognized as the potential candidate to replace SRAM. Compared with SRAM, STT-RAM has advantages of non-volatility, zero leakage power, and higher density. To further improve data density, multi-level cell (MLC) STT-RAM that can store two bits per cell has been proposed. However, writing hard bit of a cell would write its soft bit to the same value as well, which complicates the write operation of MLC STT-RAM. Although two-step transition (TT) is usually adopted to ensure the data correctness during a write operation, it incurs overhead of additional energy consumption and performance degradation. In this article, we propose the two-step elimination (TSE) scheme to eliminate TTs while ensure data integrity. By flipping hard bits of the cells that suffered from TTs, the TSE scheme could reduce TTs to soft transitions (STs) or zero transitions (ZTs), which incur much less overhead than TTs. To keep track of the flipped cells effectively, 6-bit TSE tag is introduced. We exploit tag reversing and advanced mode of the TSE scheme to further improve the performance. The experimental results showed that our scheme could reduce 61 percent TTs and achieve significant lifetime improvement, compared with conventional MLC STT-RAM (CMLC) scheme.

SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches

Spin-transfer torque RAM (STT-RAM) is a future technology for ON-chip caches. However, it suffers from high read and write error rates. Concurrently dealing with these errors is quite challenging and incurs large performance overhead. This article proposes a smartly allocating low-cost many-bit ECC (SALE) scheme, which makes use of the low-cost many-bit error correction coding (ECC) to overcome this performance overhead. The low-cost many-bit ECC can fix many errors with low logic complexity and latency overheads. However, it requires a large number of parity bits. Therefore, SALE smartly uses low-cost many-bit ECC for only a certain type of cache lines and manages the corresponding large number of parity bits in the data array. SALE also introduces an ECC-free partition to reduce the ECC storage requirement for the STT-RAM caches. The cache lines belonging to an ECC-free partition do not have dedicated storage space for the ECC parity bits, thereby reducing the ECC storage requirement for the STT-RAM caches. Our experimental results demonstrate that SALE achieves performance close to that of an error-free cache by improving performance by 13% (16%) over the baseline scheme in single-core (quad-core) systems while requiring 50% less storage space for the ECC parity bits.

Statistical Behavior Guided Block Allocation in Hybrid Cache-Based Edge Computing for Cyber-Physical-Social Systems

In Cyber-Physical-Social Systems (CPSS), large-scale data are continually generated from edge computing devices in our daily lives. These heterogeneous data collected from CPSS are urgently needed to be processed efficiently with low power consumption. Hybrid cache based edge computing can accelerate the computing speed for the edge devices. Hybrid cache consisting of spin-transfer torque RAM (STT-RAM) and static RAM (SRAM) has been proposed as last level cache (LLC) for energy efficiency recently in CPSS. However, the write operations on STT-RAM suffer from considerably higher energy consumption as well as longer latency than SRAM, the proper allocation of data blocks has a significant effect on both energy consumption and performance in the hybrid cache. So it is very useful to adjust the data allocation for the asymmetric-access in hybrid cache. To enhance the performance of hybrid cache, this paper proposes a novel statistical behavior guided block allocation (SBOA) scheme to process CPSS data. The key idea is to estimate the cache block characteristics based on the statistical behavior of data read/write re-references. We design a theoretical analysis model to optimize the energy consumption and guide block allocation in both SRAM region and STT-RAM region. Experimental results demonstrate that the proposed scheme reduces the dynamic energy consumption by 18.5%, and reduces execution time by 7.4% on average compared to the baseline with negligible overhead.

Low-Current-Density Magnetic Tunnel Junctions for STT-RAM Application Using MgO$_{{x}}$ N$_{\text{1}-{x}}\,\,({x}=\text{0.57}$ ) Tunnel Barrier

High switching speed, endurance, and low-current-based perpendicular magnetic tunnel junction (p-MTJ) memory is attracting wide interest as a key promising candidate for next-generation spintronic memory technology. p-MTJ-based spin-transfer torque RAM (STT-RAM) has been extensively investigated, and despite the promise, there is concern about the high switching current density and low stability with regard to scaling. In this work, the current controllability of p-MTJ in iron (Fe)-enriched Co20Fe60B20 with a newly designed MgO x N1– x tunnel layer is systematically investigated, with the expectation that the introduction of N minimizes the oxidation of Fe to improve the performance of the device. A facile, plasma-based oxynitridation (MgO x = 0.57N1– x =0.43) of MgO through RF-sputter deposition serves as a reliable procedure to establish a tunnel barrier for an MTJ structure fabricated with ~300-nm diameter and pinned with synthetic antiferromagnetic (SAF) [Co/Pt] ${_{n}}$ multilayer stack. Current-controlled tunneling magnetoresistance (TMR) up to ~65% was observed at room temperature (RT) with ultralow switching current density ( ${J}_{c}$ ) of 136 ± 17 kA/cm2. TMR along with tunnel conductance ( ${g}$ ( ${V}$ )) was measured to be highly stable in the read-bias regime (−200 to +200 mV) for MgO x N1– x as compared to the reported MgO barrier. The analogous MgO x N1– x -based MTJ structures were modeled using the nonequilibrium Green’s function (NEGF) with appropriate tunnel barrier parameters and incorporating modulated barrier height as compared with the MgO barrier. The current–voltage characteristics of the modeled device showed close agreement with experimental data indicating high spin current. Based on the field-induced magnetization analysis, the macro-magnetic reversal analysis suggests the free-layer switching duration of ~3 ns. These observations show the strong candidature of MgO x N1– x ( ${x} = {0.57}$ ) MTJs for STT-RAM device application.

DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories

In this paper, a data sensitive write circuit is presented to decrease the Write attempt error in STT-RAM memories. CMOS technology presents a myriad of challenges to system designers in the form of soft error reliability, volatility, power consumption, and scalability. STT-RAM (Spin Transfer Torque RAM) is one of promising non-volatile memory whose write error occurs basically due to fabrication process fluctuation. These problems which happen in different current densities made a key drawback in STT-RAM memory technologies. This paper addresses this problem and provides a solution for the drawback. A continuous and dynamic method along with the dual source approach is proposed and optimizations in physical characteristics of transistors is performed. The proposed technique can be classified into two major sections. The first section comprises of a thermal assisted circuit designed to decrease the asymmetric behaviour while writing the two states 0 and 1. A dynamic write current injector designed to hasten the write operation constitutes the subsequent section. In order to validate the design, a comparison has been made between the results of several functional simulations performed on DYSCO and the results of existing related studies. Using physical parameters optimization, we achieved WER reduction, write performance improvement and power gain. On average 27.17% improvement of write time latency is achieved with bounded 11% area overhead.

HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems

Spin-Transfer Torque RAM (STT-RAM) is widely considered a promising alternative to SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high density, and fast read speed. The STT-RAM's small feature size is particularly desirable for the last-level cache (LLC), which typically consumes a large area of silicon die. However, long write latency and high write energy still remain challenges of implementing STT-RAMs in the CPU cache. An increasingly popular method for addressing this challenge involves trading off the non-volatility for reduced write speed and write energy by relaxing the STT-RAM's data retention time. However, in order to maximize energy saving potential, the cache configurations, including STT-RAM's retention time, must be dynamically adapted to executing applications' variable memory needs. In this paper, we propose a highly adaptable last level STT-RAM cache (HALLS) that allows the LLC configurations and retention time to be adapted to applications' runtime execution requirements. We also propose low-overhead runtime tuning algorithms to dynamically determine the best (lowest energy) cache configurations and retention times for executing applications. Compared to prior work, HALLS reduced the average energy consumption by 60.57% in a quad-core system, while introducing marginal latency overhead.

Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones

This article presents a transfer learning (TL) followed by reinforcement learning (RL) algorithm mapped onto a hierarchical embedded memory system to meet the stringent power budgets of autonomous drones. The power reduction is achieved by 1. TL on meta-environments followed by online RL only on the last few layers of a deep convolutional neural network (CNN) instead of end-to-end (E2E) RL and 2. Mapping of the algorithm onto a memory hierarchy where the pre-trained weights of all the conv layers and the first few fully connected (FC) layers are stored in dense, low standby leakage Spin Transfer Torque (STT) RAM eNVM arrays and the weights of the last few FC layers are stored in the on-die SRAM. This memory hierarchy enables real-time RL as the drone explores unknown territories and the system only reads the weights from eNVM (that are slow and power hungry to write otherwise) for inference and uses the on-die SRAM for low latency training through both write and read of the weights of the last few layers. The proposed system is extensively simulated on a virtual environment and dissipates 83.5% lower energy per image frame as well as 79.4% lower latency as compared to E2E RL without any loss of accuracy. The speed of the drone is improved by a factor of $3\times $ due to higher frame rates as well.

MH Cache

Mobile devices have become the most important devices in our life. However, they are limited in battery capacity. Therefore, low-power computing is crucial for their long lifetime. A spin-transfer torque RAM (STT-RAM) has become emerging memory technology because of its low leakage power consumption. We herein propose MH cache, a multi-retention STT-RAM-based cache management scheme for last-level caches (LLC) to reduce their power consumption for mobile hardware rendering systems. We analyzed the memory access patterns of processes and observed how rendering methods affect process behaviors. We propose a cache management scheme that measures write-intensity of each process dynamically and exploits it to manage a power-efficient multi-retention STT-RAM-based cache. Our proposed scheme uses variable threshold for a process’ write-intensity to determine cache line placement. We explain how to deal with the following issue to implement our proposed scheme. Our experimental results show that our techniques significantly reduce the LLC power consumption by 32% and 32.2% in single- and quad-core systems, respectively, compared to a full STT-RAM LLC.

A Restore-Free Mode for MLC STT-RAM Caches

Spin-transfer torque RAM (STT-RAM) caches are foreseen to replace traditional static RAM caches because of their nonvolatile nature and high density. Multilevel cell (MLC) STT-RAMs further enhance the storage density of single-level cell STT-RAMs. However, the two-step read/write process in MLC STT-RAMs adversely affects performance, energy consumption, and lifetime. Moreover, technology scaling makes the read operations disturb the stored data in MLC STT-RAMs, giving rise to an issue called read disturbance (RD). Restore operations, which are required to cope with RD, further add to the problems of using MLCs. In this brief, we propose a Restore-free mode for frequently reused cache lines in MLC STT-RAMs that leverages single-step read/write operations to the MLC without the need for restore operations. Our proposed scheme in single-core (quad-core) systems, achieves a 27.4% (23%) dynamic energy reduction, a 3.7% (7%) increase in performance, and an 81% (62.5%) lifetime improvement.

(Invited) Electrochemically-Tunable and Low-Power 2D Synapses for Neuromorphic Computing

Inspired by the human brain, which is better at complex tasks such as pattern recognition than even supercomputers with much better efficiency, neuromorphic computing has recently attracted much research attention. Biological neural networks employ analog changes in neural connections strength (i.e. synaptic weight) during the decision-making and learning processes, in contrast to modern computers that use digital ‘0’ and ‘1’ for computation. However, majority of the current research efforts towards developing artificial synapses are based on digital technology with the binary SRAM, which consists 8 transistors, making it impractical to scale up the system to the level of complexity we need due to constraints in power and area. Recently, emerging nanoelectronics such as phase-change memory (PCM), oxide-based resistive random access memory (RRAM), metal-ion based electrochemical metallization memory (ECM), spin torque transfer (STT) RAM, ferroelectric FeRAM, and nano-devices have been studied for neuromorphic computing. While some of these approaches especially PCM and RRAM have demonstrated promising results to lower the power consumption and speed up the learning, they still suffer from critical issues such as insufficient precision, non-linear behaviors, and large device variations. In this work, we present a novel approach to build electrochemically-tunable, two-dimensional (2D) synapses with excellent controllability (~0.25% ΔR per switching), good energy efficiency (~500 fJ per switching), symmetric resistance response, and a rare combination of low-power programming and good retention. In our 2D synapses, the channel conductance, representing the synaptic weight in a biological synapse, can be modulated by controlling the concentration of ions between layers of graphene through a process called electrochemical intercalation. The major advantage in our approach is that we can achieve reversible and precise programming of the 2D device’s conductance to mimic synaptic plasticity with low power consumption. Unlike typical memory devices, the programming and storage mechanisms in our electrochemical synapses are decoupled, allowing us to achieve both low-power switching and good retention properties. While electrochemical intercalation has been widely used in rechargeable Li ion batteries (LIBs), this is the first demonstration of a 2D electrochemical analog memory for synaptic devices. We choose graphene in this work because graphite is a common anode material for Li ion batteries (LIBs), with good compatibility and well-characterized behaviors for Li intercalation, as illustrated in our galvanostatic discharge and in-situ Raman measurements. Through tuning the electrochemical potential of graphene, we can modulate the Li concentration and thus the electrical conductance of graphene in a continuous fashion. We perform pulse measurements (50-pA, 10-ms) to emulate the excitatory and inhibitory behavior of synapse, where we achieve ~0.25% change of channel resistance ΔR per pulse. This decrease (increase) in resistance, mimicking an increase (decrease) in synaptic weight of an excitatory (inhibitory) synapse, is the result of an increase (decrease) of Li concentration in graphene. We also achieve long-term potentiation and depression (increase and decrease in synaptic weight) through applying a series of intercalating and de-intercalating pulses. We reliably and reversibly program the graphene synapse into over 400 discrete states over our operating range. The resistance response is highly symmetric and linear. Lastly, we demonstrate spike-timing-dependent plasticity (STDP) in our synapse, where the change in resistance depends on the timing difference Δt between the pulses – similar to the biological phenomenon that the effectiveness of repeated learning depends on the duration of the gap between each stimulation. In summary, we develop an electrochemical, 2D synaptic device with low energy efficiency (500 fJ/synaptic event), precise control over synaptic conductance (0.25% ΔR per step), and good cycling performance. We demonstrate basic neuromorphic functionalities such as short-term and long-term plasticity, as well as spike-timing-dependent plasticity. This work can lead to the low-power hardware implementation of neural networks for neuromorphic computing as well as tunable 2D electronics where the material properties can be precisely engineered.