Spin-on Polymer Research Articles

Ambipolar carbon nanotube transistors with hybrid nanodielectric for low-voltage CMOS-like electronics

The proliferation of place-and-forget devices driven by the exponentially-growing Internet of Things industry has created a demand for low-voltage thin-film transistor (TFT) electronics based on solution-processible semiconductors. Amongst solution-processible technologies, TFTs based on semiconducting single-walled carbon nanotubes (sc-SWCNTs) are a promising candidate owing to their comparatively high current driving capability in their above-threshold region at low voltages, which is desirable for applications with constraints on supply voltage and switching speed. Low-voltage above-threshold operation in sc-SWCNTs is customarily achieved by using high-capacitance-density gate dielectrics such as metal-oxides fabricated via atomic layer deposition (ALD) and ion-gels. These are unattractive, as ALD requires complex-processing or exotic precursors, while ion-gels lead to slower devices with poor stability. This work demonstrates the fabrication of low-voltage above-threshold sc-SWCNTs TFTs based on a high-capacitance-density hybrid nanodielectric, which is composed of a readily-made AlO x nanolayer and a solution-processed self-assembled monolayer (SAM). The resultant TFTs can withstand a gate-channel voltage of 1–2 V, which ensures their above-threshold operation with balanced ambipolar behavior and electron/hole mobilities of 7 cm2 V−1 s−1. Key to achieving balanced ambipolarity is the mitigation of environmental factors via the encapsulation of the devices with an optimized spin-on polymer coating, which preserves the inherent properties of the sc-SWCNTs. Such balanced ambipolarity enables the direct implementation of CMOS-like circuit configurations without the use of additional dopants, semiconductors or source/drain electrode metals. The resultant CMOS-like inverters operate in the above-threshold region with supply voltages in the 1–2 V range, and have positive noise margins, gain values surpassing 80 V/V, and a bandwidth exceeding 100 kHz. This reinforces SAM-based nanodielectrics as an attractive route to easy-to-fabricate sc-SWCNT TFTs that can operate in the above-threshold region and that can meet the demand for low-voltage TFT electronics requiring moderate speeds and higher driving currents for wearables and sensing applications.

Polymer peel‐off mask for high‐resolution surface derivatization, neuron placement and guidance

We present a dry lift-off method using a chemically resistant spin-on plastic, polyimide, to pattern surfaces with high accuracy and resolution. Using well-known lithographic and reactive ion etching techniques, the spin-on polymer is patterned over a silicon dioxide surface. The plastic efficiently adheres to the silicon dioxide surface during the chemical modification and is readily lifted-off following the derivatization process, permitting highly reliable surface derivatization. The verticality of the reactive ion etch enables sub-micrometer features to be patterned, down to 0.8 µm. The technique is used to pattern neurons on silicon dioxide surfaces: efficient neuron placement over a 4 mm area is shown for patterns larger than 50 µm while process guidance is shown for 10 µm patterns.

Gapfill Study of Polyimides for MEMS Applications

Various types of polyimide have been used widely in the manufacturing of integrated circuits and MEMS’ (Micro Electrical Mechanical Systems) such as sensors. These organic spin-on polymers exhibit a wide range of mechanical and electrical properties and have been commonly used for electrical insulation as well as device passivation and protection. In addition, these organic spin-on polymers serve as excellent sacrificial materials for forming cavities on MEMS structures. This work studies the gapfill properties of several polyimides after spin-coating and curing. In addition, this work examines and compares the gapfilling and planarization properties of a number of different polyimides, including multiple layers of polyimides for gapfilling and planarization.

Fabrication and Electrical Evaluation of Via Last Polymer Liner TSVs

Imec is developing two TSV flavors for Si thicknesses of 50 and 100 μm for various wafer level packaging (WLP) applications where thin dice are stacked and electrically connected to each other through post CMOS processed TSVs and microbumps. As a differentiator, these TSV technologies use spin-on dielectric polymers as the insulating liner. A three-mask process sequence is implemented for fabrication of both TSV types; however, the TSV shape, the process flow, and the Si thickness are different for each one of them. All processes employed in the fabrication of the TSVs are performed at low temperature (<200°C) for post CMOS compatibility. For both TSV types, electrically yielding TSV connected daisy chains are measured on the fabricated wafers and the reliability of the TSVs while undergoing thermal cycle tests is analyzed.

Single-Crystalline Silicon Layer Transfer to a Flexible Substrate Using Wafer Bonding

This paper reports the successful transfer of a thin single-crystalline silicon film to a flexible, transparent polymer substrate. Thin-film silicon on polymer was realized by bonding a silicon-on-insulator (SOI) wafer to a flexible substrate using a spin-on polymer as an adhesive. The SOI wafer was thinned by a grinding operation followed by chemical mechanical polishing (CMP). The SOI was further thinned to the buried oxide using wet etchants. The residual stress in the transferred substrate was investigated by ultraviolet (UV) micro-Raman spectroscopy and numerical modeling. Both approaches showed that a low level of stress was created at the bonded interface during the layer transfer.

Via Last using Polymer Liners and their Reliability

This paper discusses the use of polymer dielectrics as insulating liner for realizing two types of 3D-WLP through Si vias (TSV's) in Si wafers with a thickness of respectively 50 and 100μm. These TSV technologies are based on thinning first, via last approach where 3D interconnects are implemented on the backside of thinned IC fabricated device wafers. Key aspects of the TSV processes are: i) fabricating the TSV from the backside of the wafer and contacting to BEOL M1, hence it is independent of the BEOL interconnect stack. ii) use of thick polymer as via isolation is a differentiator from most classical approaches using thin CVD oxide or nitride. The result is a significantly reduced capacitance, and hence, improvement of electrical performance. Another advantage of using thick polymer is that it can absorb some of the stress induced by CTE mismatch between the Cu in via and surrounding Si. This paper presents IMEC's 3D-WLP TSV flavors developed using spin-on dielectric polymers as isolation layer and the reliability of these TSVs' while undergoing thermal cycle tests. For each wafer thickness a 3-mask process sequence is implemented to fabricate the TSVs. Different process flows are used for the different Si thicknesses. For the 100μm thick substrate, a low aspect ratio TSV is used. A Si-via is etched from the wafer backside with a bottom diameter of about 70μm. The top side of the via is chamfered and has a top diameter of about 100μm. As a dielectric liner, a photo-sensitive spin-on polymer is conformally coated on the wafer. At the via bottom, a contact hole with approximately 30μm diameter is realized by photo patterning. Next, conformal Cu plating is used as TSV metallization. For the 50μm thick substrates, a different approach is used enabling a higher aspect ratio TSV. First, a 5μm wide ring trench is etched in the Si. Subsequently, these trenches are filled with a spin-on polymer. After filling the ring trenches, the central Si pillar is etched out of the via (second litho step) and the oxide at the via bottom is removed to provide access to the lowest chip metal level. Next, bottom-up Cu via fill is used to form the TSV metallization. This via has a Cu TSV diameter of 25μm, and an overall diameter with isolation of 35μm [1]. All processes employed in the fabrication of the TSVs are performed at low temperature (<200°C) for maximum post CMOS compatibility The test vehicle used to develop the TSV technologies include TSV daisy chains of various lengths connecting different number of vias to determine the TSV yield and resistance. For both TSV approaches, yielding electrical measurements are done on fabricated TSV wafers. For 50μm thick silicon, up to 95% electrical yield is achieved and the single TSV resistance is measured to be ~10–15mΩ on bonded stacks through Kelvin structures. Thermal cycling from −40 to +125°C of TSV dies are also done, and after 1000 thermal cycles no electrical failure is observed. For 100μm thick silicon TSV approach, single TSV resistance is measured to be ~4–20mΩ with good yield. Test die are subjected to 1000 thermal cycles and results show limited yield loss.

Fully automated hot embossing processes utilizing high resolution working stamps

Nanoimprint lithography is a fast replication technology for structures with sizes ranging from micrometer down to few nanometer range. This article describes the technology for imprinting of polymer substrates as well as spin-on polymers by using soft working stamp materials on a fully automated hot embossing system, the EVG®750, built to use this rapid replication processes. By utilizing soft working stamps, the authors demonstrate the possibility to replicate, in fully automated mode, both high-aspect ratio features in thermoplastic materials as needed for microfluidic lab-on-chip applications as well as high resolution features down to 50nm in polymer that can be used as templates for pattern transfer in the fabrication of plasmonic substrates for biosensing applications.

ALX Polymer for Wafer Level Packaging: Mechanical Property Evaluation After Multiple Lead-Free Solder Reflows

For bumping and wafer level packaging (WLP) applications, BCB and polyimide are the predominant spin-on dielectric materials used for re-passivation, redistribution, interlayer dielectric, and stress buffer layers. Each of these materials has their respective strengths and weaknesses. BCB has exceptionally low shrinkage on cure and moisture absorption, low curing temperature, and a low dielectric constant, but is a mechanically brittle material which limits its application in bump-on-polymer applications. Polyimides are superior mechanically to BCB and are utilized more in bump-on-polymer structures, but suffer from much higher shrinkage on cure and moisture absorption (which can lead to blistering if not carefully processed), have higher dielectric constants, and have much higher cure temperatures. ALX spin-on polymer dielectric was developed to combine low shrinkage, low moisture absorption, low dielectric constant, and excellent mechanical and stress buffering properties with a cure temperature between 190C to 250C, depending on the application(1-3). Previous papers have reported the mechanical properties at 190C and the application of ALX in eutectic SnPb solder bump structures. The use of lead-free solder requires reflow temperatures up to 260C. Although ALX polymer is curable at less than 200C, the influence of lead-free solder reflow wasnft investigated. In this presentation we evaluate mechanical property changes of ALX Polymer films after different cure schedules and multiple reflows at lead-free solder temperatures. The impact of these parameters on WLP will be discussed.

Fully automated hot embossing processes utilizing high resolution working stamps

Nanoimprint lithography (NIL) is a fast replication technology for structures with sizes ranging from micrometer down to few nanometers range. This paper describes the technology for imprinting of polymer substrates as well as spin-on polymers by using soft working stamp materials. A fully automated hot embossing system, the EVG®750 was built to use this rapid replication processes. By utilizing soft working stamps, we demonstrate the possibility to replicate, in fully automated mode, both high-aspect ratio features in thermoplastic materials as needed for microfluidic lab-on-chip applications as well as high resolution features down to 50 nm in polymer that can be used as templates for pattern transfer in the fabrication of plasmonic substrates for bio-sensing applications.

Photo-definable microchannels made with spin-on polymers and short sacrificial etch times

Hollow tubular microfluidic channels were fabricated from two spin-on, photodefinable polymers.

Acoustic transducers with a perforated damping backplate based on PZT/silicon wafer bonding technique

This paper reports on a membrane-type acoustic transducer fabricated by bonding a piezoelectric ceramic Pb(Zr,Ti)O 3 (PZT) plate to a silicon on insulator (SOI) wafer. A special Si backplate with perforated acoustic holes is also bonded to the membrane to broaden the acoustic frequency spectrum. Key techniques in the fabrication include a low-temperature bonding technique using a spin-on polymer, design of electrode interconnect, chemical mechanical polishing (CMP) for thinning down the bulk PZT, and deep reactive ion etching bulk micromachining of silicon. High quality integrated transducers on SOI wafer have been successfully demonstrated and the fabrication and measurement results are presented.

Fabrication of 200nm period blazed transmission gratings on silicon-on-insulator wafers

The authors report on the fabrication of 200nm period blazed transmission gratings on silicon-on-insulator (SOI) wafers. These critical angle transmission (CAT) gratings require 3–5μm tall freestanding grating bars with a very high aspect ratio (>100) and smooth sidewalls. In order to meet the challenging geometrical requirements, they modified and improved our previously reported process for the fabrication of a CAT grating prototype with 574nm period. They have used potassium hydroxide (KOH) solutions to fabricate high aspect ratio gratings on ⟨110⟩ SOI wafers. The KOH etching process was improved to minimize the lateral undercut through precise grating alignment to ⟨111⟩ planes within ±0.05° and a room temperature etch process with 50wt% KOH. In addition, an image-reversal technique with a high silicon content spin-on polymer was applied to increase process latitude with a high duty cycle nitride mask. A surfactant was also added to the KOH solution to promote hydrogen bubble release. With the improved process, they achieved a high etch anisotropy of above 300 on a ⟨110⟩ silicon wafer. They successfully fabricated 200nm period CAT gratings with support mesh periods of 25 and 40μm in a 9mm2 area of 4-μm-thick silicon membranes on ⟨110⟩ SOI wafers.

Integrated miniaturized optical detection platform for fluorescence and absorption spectroscopy

This paper presents the design and fabrication of a miniaturized optical detection system for sensing in microchannels, based on integrated optical waveguide technology. This design allows the implementation of both absorption and fluorescence measurement schemes and can be potentially integrated into a lab-on-a-chip system. An array of optical waveguides were fabricated in spin-on polymer technology on a silicon substrate and monolithically integrated with the microfluidic channel and V-groove fibre alignment scheme. The design was adapted to achieve minimum optical losses under the imposed fabrication constraints. Total system losses with a water filled microchannel were experimentally determined to be 10.45dB. Both fluorescence and absorption detection capabilities of the fabricated device were demonstrated using Alexa Fluor 633 dye, and the corresponding detection limits were found to be 10nM and 1μM, respectively. Several areas of improvements in the device design and fabrication have been identified for future works towards better integration for lab-on-a-chip system.

65.2: Spin-On Polymers for TFT Gate Dielectric Application and Planarization of Stainless Steel

We present spin-on polymer films with significantly improved dielectric properties for TFT gate dielectric applications. Breakdown voltage//leakage current//CV hysteresis are 4.10 MV/cm at 1 μA/cm2//4.9 × 10−8 A/cm2 at 2.5 MV/cm//3.4 V and 4.73 MV/cm//2.6 × 10−8 A/cm2//0.44V at curing temperatures of 250 °C and 425 °C, respectively. In addition, we present our recent results using spin-on dielectrics to planarize and insulate stainless steel substrates for flexible displays and high resolution QVGA mobile displays.

Spin-on Gate Dielectric Materials for Next Generation Display Systems

ABSTRACTWe present recent advances on spin-on polymers as gate dielectric for thin film transistors. We have developed film type I with significantly improved dielectric properties. At a curing temperature of 250 °C, the dielectric constant is 3.46, the breakdown voltage is 4.10 MV/cm at 1 μA/cm2, the leakage current is 4.9 × 10−8 A/cm2 at 2.5 MV/cm, and the CV hysteresis is 3.4 V. At a curing temperature of 425 °C, the dielectric constant, the breakdown voltage, the leakage current, and the CV hysteresis are 3.2, 4.73 MV/cm, 2.6 × 10−8 A/cm2, and 0.44 V respectively.

Self-Aligning Planarization and Passivation for Integration Applications in III–V Semiconductor Devices

This work reports an easy planarization and passivation approach for the integration of III-V semiconductor devices. Vertically etched III-V semiconductor devices typically require sidewall passivation to suppress leakage currents and planarization of the passivation material for metal interconnection and device integration. It is, however, challenging to planarize all devices at once. This technique offers wafer-scale passivation and planarization that is automatically leveled to the device top in the 1-3-/spl mu/m vicinity surrounding each device. In this method, a dielectric hard mask is used to define the device area. An undercut structure is intentionally created below the hard mask, which is retained during the subsequent polymer spinning and anisotropic polymer etch back. The spin-on polymer that fills in the undercut seals the sidewalls for all the devices across the wafer. After the polymer etch back, the dielectric mask is removed leaving the polymer surrounding each device level with its device top to atomic scale flatness. This integration method is robust and is insensitive to spin-on polymer thickness, polymer etch nonuniformity, and device height difference. It prevents the polymer under the hard mask from etch-induced damage and creates a polymer-free device surface for metallization upon removal of the dielectric mask. We applied this integration technique in fabricating an InP-based photonic switch that consists of a mesa photodiode and a quantum-well waveguide modulator using benzocyclobutene (BCB) polymer. We demonstrated functional integrated photonic switches with high process yield of >90%, high breakdown voltage of >25 V, and low ohmic contact resistance of /spl sim/10 /spl Omega/. To the best of our knowledge, such an integration of a surface-normal photodiode and a lumped electroabsorption modulator with the use of BCB is the first to be implemented on a single substrate.

Reactive Ion Etching and Characterization of p-Silk Ultra Low-k Film

Reactive ion etch (RIE) of p-SiLK, a spin-on polymer based ultra low-k (ULK) material with a k value of /spl sim/2.2 was characterized and its influence on electrical yield and dielectric breakdown is presented here. Material characterization was done using blanket films after curing and the effect of exposure to different conventional plasma etch gas mixtures was studied for surface composition, roughness and dielectric constant. Trench etch process was developed for 130-nm technology node for single damascene process integration. Dual hard mask approach was taken and two etch schemes viz., etching under hardmask and etching under photoresist were evaluated. In both schemes, trench etch profiles were near vertical and critical dimension (CD) control was within 10%. RIE lag and the carbon depletion at the sidewalls were found to be insignificant confirming acceptable etch process performance. Etching under photoresist scheme was found advantageous in terms of trench profile for isolated structures, reduced cycle time making the process cost effective and reduced post-CMP defects. However, from the comparison of electrical test results, etch under hardmask scheme showed higher electrical yield and better performance than etch under PR scheme. Although trench sidewalls were exposed to plasma during both schemes, sidewall damage did not contribute to overall leakage. The RIE process developed and the characterization results have confirmed the compatibility of material and RIE process for successful process integration.

High Strength Low Dielectric Constant Aromatic Thermosets

AbstractContinuing miniaturization of microelectronic devices requires development of low dielectric constant materials to lower the RC delay, power dissipation and crosstalk noise. Although spin-on polymer dielectrics usually have better potential for extendibility to lower dielectric constant (k) values compared to chemical-vapor-deposited dielectrics, their low mechanical properties prevent them from being successfully integrated with copper metal lines.Recent evaluation of a new thermosetting oligomer shows high thermal stability, low moisture pick-up and low dielectric constant. Techniques to optimize the solubility and spin coating characteristics of the oligomer have been developed. The thermally cured polymer displayed a thermal stability up to 480°C in nitrogen and 400°C in air. The cured polymer displayed a dielectric constant of 2.7 at 1 MHz and a breakdown strength larger than 230 V/μm. Nanoindentation testing showed that it had an extraordinarily high Young's modulus of 16.8 GPa and a hardness of 3.5 GPa. By use of porogens, a dielectric constant as low as 1.85 was obtained while still maintaining an acceptable high Young's modulus of 7.7 GPa and hardness of 2.0 GPa. Nanoscratch testing indicated that this material had good adhesion to the Si substrate, and Ta which is a diffusion barrier for copper. These results appear unique compared to all commercially available low-k candidates.

Adhesion of Cu and low-k Dielectric Thin Films with Tungsten Carbide

The adhesion of copper and various dielectric materials to tungsten carbide was studied using interfacial critical debond energies obtained by the four-point flexure method. Tungsten carbide (W2C), films 33.3 nm thick, were vapor deposited onto SiO2, spin-on carbon polymer resin (CPR), chemically vapor deposited organosilicate glass (OSG), and spin-on siloxane-organic polymer (SOP) surfaces using direct-current magnetron sputtering of a W metal target and a methane substrate plasma. Thick copper films (42.5 nm) were vapor deposited onto W2C. Some interfaces were modified by an Ar plasma, 1-nm W deposition, or O2 plasma treatment prior to Cu deposition. A W2C film deposited onto a CPR substrate was annealed for 2 h at 673 K in a 99% N2/1% H2gas mixture. For the untreated dielectric surfaces, the debond energy ranged from 39.9 to 3.95 J/m2. In order of descending adhesion energy, the substrates are ranked CPR, SiO2, SOP, and OSG. Ar plasma treatment of the SiO2 surface increased the debond energy from 20.3 to 41.3 J/m2. The Cu/W2C debond energy was 20.4 J/m2. Ar plasma or 1-nm W deposition treatment to the carbide surface moved the point of delamination from the Cu/W2C interface to the W2C/CPR interface for a Cu/W2C/CPR multilayer structure.

A low-temperature bonding technique using spin-on fluorocarbon polymers to assemble microsystems

A new low-temperature biochemically compatible polymer bonding process has been successfully developed. The bonding has been characterized for bond strength and chemical resistance. This technique has successfully addressed a major challenge in the development of microfluidic systems from discrete components by enabling the bonding of the components to the microfluidic motherboards at low temperatures and ensuring reliable, leak-proof and chemically inert bonding. This bonding technique uses a spin-on Teflon-like amorphous fluorocarbon polymer. The bonding technique lowers the bonding temperature (∼160 °C), shows a good bond strength of 4.3 MPa in silicon-to-silicon, and has excellent chemical resistance to various chemicals used in microelectromechanical systems processing.