Spike Sorting System Research Articles

An unsupervised real-time spike sorting system based on optimized OSort

Objective. The OSort algorithm, a pivotal unsupervised spike sorting method, has been implemented in dedicated hardware devices for real-time spike sorting. However, due to the inherent complexity of neural recording environments, OSort still grapples with numerous transient cluster occurrences during the practical sorting process. This leads to substantial memory usage, heavy computational load, and complex hardware architectures, especially in noisy recordings and multi-channel systems. Approach. This study introduces an optimized OSort algorithm (opt-OSort) which utilizes correlation coefficient (CC), instead of Euclidean distance as classification criterion. The CC method not only bolsters the robustness of spike classification amidst the diverse and ever-changing conditions of physiological and recording noise environments, but also can finish the entire sorting procedure within a fixed number of cluster slots, thus preventing a large number of transient clusters. Moreover, the opt-OSort incorporates two configurable validation loops to efficiently reject cluster outliers and track recording variations caused by electrode drifting in real-time. Main results. The opt-OSort significantly reduces transient cluster occurrences by two orders of magnitude and decreases memory usage by 2.5–80 times in the number of pre-allocated transient clusters compared with other hardware implementations of OSort. The opt-OSort maintains an accuracy comparable to offline OSort and other commonly-used algorithms, with a sorting time of 0.68 µs as measured by the hardware-implemented system in both simulated datasets and experimental data. The opt-OSort’s ability to handle variations in neural activity caused by electrode drifting is also demonstrated. Significance. These results present a rapid, precise, and robust spike sorting solution suitable for integration into low-power, portable, closed-loop neural control systems and brain–computer interfaces.

Edge computing on TPU for brain implant signal analysis

The ever-increasing number of recording sites of silicon-based probes imposes a great challenge for detecting and evaluating single-unit activities in an accurate and efficient manner. Currently separate solutions are available for high precision offline evaluation and separate solutions for embedded systems where computational resources are more limited.We propose a deep learning-based spike sorting system, that utilizes both unsupervised and supervised paradigms to learn a general feature embedding space and detect neural activity in raw data as well as predict the feature vectors for sorting. The unsupervised component uses contrastive learning to extract features from individual waveforms, while the supervised component is based on the MobileNetV2 architecture. One of the key advantages of our system is that it can be trained on multiple, diverse datasets simultaneously, resulting in greater generalizability than previous deep learning-based models.We demonstrate that the proposed model does not only reaches the accuracy of current state-of-art offline spike sorting methods but has the unique potential to run on edge Tensor Processing Units (TPUs), specialized chips designed for artificial intelligence and edge computing. We compare our model performance with state of art solutions on paired datasets as well as on hybrid recordings as well. The herein demonstrated system paves the way to the integration of deep learning-based spike sorting algorithms into wearable electronic devices, which will be a crucial element of high-end brain–computer interfaces.

Partially binarized neural networks for efficient spike sorting.

While brain-implantable neural spike sorting can be realized using efficient algorithms, the presence of noise may make it difficult to maintain high-peformance sorting using conventional techniques. In this article, we explore the use of partially binarized neural networks (PBNNs), to the best of our knowledge for the first time, for sorting of neural spike feature vectors. It is shown that compared to the waveform template-based methods, PBNNs offer robust spike sorting over various datasets and noise levels. The ASIC implementation of the PBNN-based spike sorting system in a standard 180-nm CMOS process is presented. The post place and route simulations results show that the synthesized PBNN consumes only 0.59 W of power from a 1.8 V supply while operating at 24 kHz and occupies 0.15 mm of silicon area. It is shown that the designed PBNN-based spike sorting system not only offers comparable accuracy to the state-of-the-art spike sorting systems over various noise levels and datasets, it also occupies a smaller silicon area and consumes less power and energy. This makes PBNNs a viable alternative towards the implementation of brain-implantable spike sorting systems.

ELVISort: encoding latent variables for instant sorting, an artificial intelligence-based end-to-end solution

Objective. The growing number of recording sites of silicon-based probes means that an increasing amount of neural cell activities can be recorded simultaneously, facilitating the investigation of underlying complex neural dynamics. In order to overcome the challenges generated by the increasing number of channels, highly automated signal processing tools are needed. Our goal was to build a spike sorting model that can perform as well as offline solutions while maintaining high efficiency, enabling high-performance online sorting. Approach. In this paper we present ELVISort, a deep learning method that combines the detection and clustering of different action potentials in an end-to-end fashion. Main results. The performance of ELVISort is comparable with other spike sorting methods that use manual or semi-manual techniques, while exceeding the methods which use an automatic approach: ELVISort has been tested on three independent datasets and yielded average F1 scores of 0.96, 0.82 and 0.81, which comparable with the results of state-of-the-art algorithms on the same data. We show that despite the good performance, ELVISort is capable to process data in real-time: the time it needs to execute the necessary computations for a sample of given length is only 1/15.71 of its actual duration (i.e. the sampling time multiplied by the number of the sampling points). Significance. ELVISort, because of its end-to-end nature, can exploit the massively parallel processing capabilities of GPUs via deep learning frameworks by processing multiple batches in parallel, with the potential to be used on other cutting-edge AI-specific hardware such as TPUs, enabling the development of integrated, portable and real-time spike sorting systems with similar performance to offline sorters.

Power-efficient Spike Sorting Scheme Using Analog Spiking Neural Network Classifier

The method to map the neural signals to the neuron from which it originates is spike sorting. A low-power spike sorting system is presented for a neural implant device. The spike sorter constitutes a two-step trainer module that is shared by the signal acquisition channel associated with multiple electrodes. A low-power Spiking Neural Network (SNN) module is responsible for assigning the spike class. The two-step shared supervised on-chip training module is presented for improved training accuracy for the SNN. Post implant, the relatively power-hungry training module can be activated conditionally based on a statistics-driven retraining algorithm that allows on the fly training and adaptation. A low-power analog implementation for the SNN classifier is proposed based on resistive crossbar memory exploiting its approximate computing nature. Owing to the direct mapping of SNN functionality using physical characteristics of devices, the analog mode implementation can achieve ∼21 × lower power than its fully digital counterpart. We also incorporate the effect of device variation in the training process to suppress the impact of inevitable inaccuracies in such resistive crossbar devices on the classification accuracy. A variation-aware, digitally calibrated analog front-end is also presented, which consumes less than ∼50 nW power and interfaces with the digital training module as well as the analog SNN spike sorting module. Hence, the proposed scheme is a low-power, variation-tolerant, adaptive, digitally trained, all-analog spike sorter device, applicable to implantable and wearable multichannel brain-machine interfaces.

Neural Spike Sorting Using Binarized Neural Networks

This article presents the design and efficient hardware implementation of binarized neural networks (BNNs) for brain-implantable neural spike sorting. In contrast to the conventional artificial neural networks (ANNs), in which the weights and activation functions of neurons are represented using real values, the BNNs utilize binarized weights and activation functions to dramatically reduce the memory requirement and computational complexity of the ANNs. The designed BNN is trained using several realistic neural datasets to verify its accuracy for neural spike sorting. The application-specific integrated circuit (ASIC) implementation of the designed BNN in a standard 0.18- [Formula: see text] CMOS process occupies 0.33 mm 2 of silicon area. Power consumption estimation of the ASIC layout shows that the BNN dissipates [Formula: see text] of power from a 1.8 V supply while operating at 24 kHz. The designed BNN-based spike sorting system is also implemented on a field-programmable gate array and is shown to reduce the required on-chip memory by 89% compared to those of the alternative state-of-the-art spike sorting systems. To the best of our knowledge, this is the first work employing BNNs for real-time in vivo neural spike sorting.

Spatial Information Based OSort for Real-Time Spike Sorting Using FPGA

Spiking activity of individual neurons can be separated from the acquired multi-unit activity with spike sorting methods. Processing the recorded high-dimensional neural data can take a large amount of time when performed on general-purpose computers. In this paper, an FPGA-based real-time spike sorting system is presented which takes into account the spatial correlation between the electrical signals recorded with closely-packed recording sites to cluster multi-channel neural data. The system uses a spatial window-based version of the Online Sorting algorithm, which uses unsupervised template-matching for clustering. The test results show that the proposed system can reach an average accuracy of 86% using simulated data (16-32 neurons, 4-10dB Signal-to-Noise Ratio), while the single-channel clustering version achieves only 74% average accuracy in the same cases on a 128-channel electrode array. The developed system was also tested on in vivo cortical recordings obtained from an anesthetized rat. The proposed FPGA-based spike sorting system can process more than 11000 spikes/second, so it can be used during in vivo experiments providing real-time feedback on the location and electrophysiological properties of well-separable single units. The proposed spike sorting system could be used to reduce the positioning error of the closely-packed recording site during a neural measurement.

Low-latency single channel real-time neural spike sorting system based on template matching.

Recent technical advancements in neural engineering allow for precise recording and control of neural circuits simultaneously, opening up new opportunities for closed-loop neural control. In this work, a rapid spike sorting system was developed based on template matching to rapidly calculate instantaneous firing rates for each neuron in a multi-unit extracellular recording setting. Cluster templates were first generated by a desktop computer using a non-parameter spike sorting algorithm (Super-paramagnetic clustering) and then transferred to a field-programmable gate array digital circuit for rapid sorting through template matching. Two different matching techniques–Euclidean distance (ED) and correlational matching (CM)–were compared for the accuracy of sorting and the performance of calculating firing rates. The performance of the system was first verified using publicly available artificial data and was further confirmed with pre-recorded neural spikes from an anesthetized Mongolian gerbil. Real-time recording and sorting from an awake mouse were also conducted to confirm the system performance in a typical behavioral neuroscience experimental setting. Experimental results indicated that high sorting accuracies were achieved for both template-matching methods, but CM can better handle spikes with non-Gaussian spike distributions, making it more robust for in vivo recording. The technique was also compared to several other off-line spike sorting algorithms and the results indicated that the sorting accuracy is comparable but sorting time is significantly shorter than these other techniques. A low sorting latency of under 2 ms and a maximum spike sorting rate of 941 spikes/second have been achieved with our hybrid hardware/software system. The low sorting latency and fast sorting rate allow future system developments of neural circuit modulation through analyzing neural activities in real-time.

A Real-Time Spike Sorting System Using Parallel OSort Clustering.

This article presents an efficient design and implementation of a real-time spike sorting system using unsupervised clustering. We utilize the online sorting (OSort) algorithm and model it first in both floating-point and fixed-point numerical representations to accurately assess the feasibility of our hardware architecture and also reliably analyze the sorting accuracy. For efficient hardware realization of OSort, we propose a modified parallel OSort algorithm. By reducing the number of required memory accesses, the number of computations performed for the management and upkeep of cluster averages and cluster merging is substantially reduced. By limiting the number of supported clusters per channel, the classification/clustering latency is significantly reduced compared to the previously published work, making the designed OSort system applicable for in-vivo spike sorting. The proposed OSort hardware architecture utilizes a novel memory configuration scheme to parallelize the OSort algorithm, which allows us to avoid using relatively large memory queues for storing detected spike waveforms and process them concurrently to the spike cluster management. The characteristics and implementation results of the designed OSort-based spike sorting system on a Xilinx Artix-7 field-programmable gate array (FPGA) are presented. The ASIC implementation of the designed system is estimated to occupy 2.57 mm2 in a standard 32-nm CMOS process. Post-layout power estimation shows that the ASIC will dissipate 2.78mW, while operating at 24kHz.

An Efficient Hardware Architecture for Template Matching-Based Spike Sorting.

This paper presents an efficient hardware architecture for the design and implementation of a spike sorting system using online template matching. Over the past decade, various spike sorting algorithms have been proposed; however, due to their computational complexity, they may not be suitable for implantable devices that have stringent area and power consumption requirements. We first developed a software-based spike sorting system in both floating-point and fixed-point representations. Then, we used our developed software-based spike sorting system for: 1) studying various neural signal processing algorithms and assessing their feasibility for efficient hardware implementations; and 2) offline processing of previously recorded neural data and extracting the threshold data and spike templates for configuring our spike sorting hardware architecture. The characteristics and implementation results of the designed spike sorting system on a Xilinx Artix-7 A200TFBG676-2 field-programmable gate array are presented. The application-specific integrated circuit (ASIC) implementation of the designed spike sorting system is estimated to occupy 0.3 mm2. Postlayout synthesis and simulation shows that the ASIC implementation will dissipate 64 nW from a 0.25-V supply, while operating at a 24-kHz frequency in a standard 45-nm CMOS technology. Compared to the previously published work, our ASIC implementation consumes 96.8% less power, while maintaining a comparable sorting accuracy. Moreover, our design can run at a higher clock frequency and uses fewer hardware resources, while achieving a 168% reduction in output data rate when comparing the raw data sampling rate and the sorted spike output rate and, yet, offers comparable spike sorting accuracy.

Real-Time Neural Signal Sensing and Spike Sorting System Using Modified Zero-Crossing Feature with Highly Efficient Data Computation and Transmission

Real-Time Neural Signal Sensing and Spike Sorting System Using Modified Zero-Crossing Feature with Highly Efficient Data Computation and Transmission

An analogue front-end model for developing neural spike sorting systems.

In spike sorting systems, front-end electronics is a crucial pre-processing step that not only has a direct impact on detection and sorting accuracy, but also on power and silicon area. In this work, a behavioural front-end model is proposed to assess the impact of the design parameters (including signal-to-noise ratio, filter type/order, bandwidth, converter resolution/rate) on subsequent spike processing. Initial validation of the model is provided by applying a test stimulus to a hardware platform and comparing the measured circuit response to the expected from the behavioural model. Our model is then used to demonstrate the effect of the Analogue Front-End (AFE) on subsequent spike processing by testing established spike detection and sorting methods on a selection of systems reported in the literature. It is revealed that although these designs have a wide variation in design parameters (and thus also circuit complexity), the ultimate impact on spike processing performance is relatively low (10-15%). This can be used to inform the design of future systems to have an efficient AFE whilst also maintaining good processing performance.

Action Potential Waveform Variability Limits Multi-Unit Separation in Freely Behaving Rats

Extracellular multi-unit recording is a widely used technique to study spontaneous and evoked neuronal activity in awake behaving animals. These recordings are done using either single-wire or mulitwire electrodes such as tetrodes. In this study we have tested the ability of single-wire electrodes to discriminate activity from multiple neurons under conditions of varying noise and neuronal cell density. Using extracellular single-unit recording, coupled with iontophoresis to drive cell activity across a wide dynamic range, we studied spike waveform variability, and explored systematic differences in single-unit spike waveform within and between brain regions as well as the influence of signal-to-noise ratio (SNR) on the similarity of spike waveforms. We also modelled spike misclassification for a range of cell densities based on neuronal recordings obtained at different SNRs. Modelling predictions were confirmed by classifying spike waveforms from multiple cells with various SNRs using a leading commercial spike-sorting system. Our results show that for single-wire recordings, multiple units can only be reliably distinguished under conditions of high recording SNR (≥4) and low neuronal density (≈20,000/ mm3). Physiological and behavioural changes, as well as technical limitations typical of awake animal preparations, reduce the accuracy of single-channel spike classification, resulting in serious classification errors. For SNR <4, the probability of misclassifying spikes approaches 100% in many cases. Our results suggest that in studies where the SNR is low or neuronal density is high, separation of distinct units needs to be evaluated with great caution.

Fuzzy logic-based spike sorting system

We present a new method for autonomous real-time spike sorting using a fuzzy logic inference engine. The engine assigns each detected event a ‘spikiness index’ from zero to one that quantifies the extent to which the detected event is like an ideal spike. Spikes can then be sorted by simply clustering the spikiness indices. The sorter is defined in terms of natural language rules that, once defined, are static and thus require no user intervention or calibration. The sorter was tested using extracellular recordings from three animals: a macaque, an owl monkey and a rat. Simulation results show that the fuzzy sorter performed equal to or better than the benchmark principal component analysis (PCA) based sorter. Importantly, there was no degradation in fuzzy sorter performance when the spikes were not temporally aligned prior to sorting. In contrast, PCA sorter performance dropped by 27% when sorting unaligned spikes. Since the fuzzy sorter is computationally trivial and requires no spike alignment, it is suitable for scaling into large numbers of parallel channels where computational overhead and the need for operator intervention would preclude other spike sorters.

Coding of spatial information by soma and dendrite of pyramidal cells in the hippocampal CA1 of behaving rats

The soma and dendrite of a single neuron differ markedly in their anatomical and chemical organization. However, the difference between the neuronal codes by the soma and dendrite in the brain of behaving animals remains unknown. Here, we show that in the hippocampal CA1 of behaving rats, the soma and dendrite of pyramidal cells code distinct spatial information. To detect these neuronal codes, we used a unique extracellular multiunit recording technique with special electrodes (dodecatrodes) and a novel spike-sorting system with an independent component analysis (ICSort). First, we examined whether ICSort could separate extracellular signals from the soma and those from the dendrite of a single cell, in comparison with the separation obtained by a conventional spike-sorting technique. The results suggest that ICSort could distinguish extracellular signals originating from the soma and dendrite. Second, we examined spatial information coded by signals from the soma and dendrite of hippocampal pyramidal cells when the rats were moving in a familiar open environment. The results indicate that the somatic units had single place fields, and showed higher spatial specificity, lower sparsity and lower firing rates than the dendritic units. Therefore, we conclude that a hippocampal pyramidal cell has the ability to transform redundant spatial information received from upstream neurons via the dendrite into more place-specific information along the dendrosomatic axis and transmit this information to downstream neurons via the soma.

A New Action Potential Detector Using the MTEO and Its Effects on Spike Sorting Systems at Low Signal-to-Noise Ratios

This paper considers neural signal processing applied to extracellular recordings, in particular, unsupervised action potential detection at a low signal-to-noise ratio. It adopts the basic framework of the multiresolution Teager energy operator (MTEO) detector, but presents important new results including a significantly improved MTEO detector with some mathematical analyses, a new alignment technique with its effects on the whole spike sorting system, and a variety of experimental results. Specifically, the new MTEO detector employs smoothing windows normalized by noise power derived from mathematical analyses and has an improved complexity by utilizing the sampling rate. Experimental results prove that this detector achieves higher detection ratios at a fixed false alarm ratio than the TEO detector and the discrete wavelet transform detector. We also propose a method that improves the action potential alignment performance. Observing that the extreme points of the MTEO output are more robust to the background noise than those of the action potentials, we use the MTEO output for action potential alignment. This brings not only noticeable improvement in alignment performance but also quite favorable influence over the classification performance. Accordingly, the proposed detector improves the performance of the whole spike sorting system. We verified the improvement using various modeled neural signals and some real neural recordings.

Employing ICA and SOM for spike sorting of multielectrode recordings from CNS

For classification of action potential shapes in multineuron recordings, we present a spike sorting system employing independent component analysis (ICA) and an unsupervised artificial neural network (Kohonen’s self-organizing map, SOM). We focus on how ICA in the first stage of the spike sorting system can be used to address specific problems arising in recordings using multielectrode arrays in the CNS. Using real data recorded from the pontine nuclei in rats and simulated data, we evaluate the performance of several ICA algorithms to remove cross-talk between electrodes using data from continuous recording (or simulation). When using cut-out data, the standard format of extracellular spike recordings, new problems emerge and robust algorithms are needed. We demonstrate that several ICA algorithms show a good performance on cut-out data from multielectrode array recordings (simulated and real data). In tetrode recordings the same neuron is purposely recorded by several electrodes simultaneously and we show, how independent component analysis can be used in this case to identify redundant information and hence to compress relevant information, improving subsequent clustering of a SOM.

Comparison of optimal and suboptimal spike sorting algorithms to theoretical limits

Often in extracellular recordings the activity of multiple units is recorded. “Spike sorting” is the process of determining the time of occurrence of each unit's action potentials. In this work, we suggest a framework for bounding the performance of spike sorting algorithms in terms of the mean squared estimation error. We examine the suitability of two theoretical bounds, the Cramér–Rao bound and the Ziv–Zakai bound. We compare the empirical performance of the optimal spike sorting system and a suboptimal scheme to the theoretical limits in two examples.