Abstract

This article presents the design and efficient hardware implementation of binarized neural networks (BNNs) for brain-implantable neural spike sorting. In contrast to the conventional artificial neural networks (ANNs), in which the weights and activation functions of neurons are represented using real values, the BNNs utilize binarized weights and activation functions to dramatically reduce the memory requirement and computational complexity of the ANNs. The designed BNN is trained using several realistic neural datasets to verify its accuracy for neural spike sorting. The application-specific integrated circuit (ASIC) implementation of the designed BNN in a standard 0.18- [Formula: see text] CMOS process occupies 0.33 mm 2 of silicon area. Power consumption estimation of the ASIC layout shows that the BNN dissipates [Formula: see text] of power from a 1.8 V supply while operating at 24 kHz. The designed BNN-based spike sorting system is also implemented on a field-programmable gate array and is shown to reduce the required on-chip memory by 89% compared to those of the alternative state-of-the-art spike sorting systems. To the best of our knowledge, this is the first work employing BNNs for real-time in vivo neural spike sorting.

Highlights

  • T HE human brain is composed of billions of neurons, communicating with one another via electro-chemical processes

  • Even though recent improvements to the k-means algorithm involve computing relatively accurate approximations of the cluster centroids using a small number of data samples [28], the memory and computational requirements of processing high-dimensional data, such as neural spike waveforms, are still not adequate for area- and power-constrained brain-implantable application-specific integrated circuit (ASIC)

  • The training time for large-scale and deep neural network models could be considerable, we found that since our model is relatively small, increasing the number of clusters (NOCs), which increases the number of artificial neurons (ANs) in the output layer, has a relatively small impact on the training time

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Summary

INTRODUCTION

T HE human brain is composed of billions of neurons, communicating with one another via electro-chemical processes. Recent hardware implementations of spike sorting aim to perform the required neural signal processing algorithms either as a supervised process, which requires some level of initial offline processing [2], or as a fully automated unsupervised process [3] in real-time [2]–[12]. The designs which require pre-processing aim to reduce the computational complexity and silicon area and power consumption significantly, by performing a set of algorithms offline on a computer to estimate the design parameters for the real-time operation of the in vivo spike sorting system. This article introduces the application of BNNs for spike sorting in an effort to significantly reduce the computational complexity and memory requirement of the system, while utilizing an initial off-line parameter estimation. The feasibility of the brain-implantable BNNbased spike sorting system for real-time processing of neural signals is discussed.

SPIKE SORTING
BINARIZED NEURAL NETWORKS FOR SPIKE SORTING
BNN HARDWARE ARCHITECTURE
Findings
CONCLUSION
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