Implementation of Single Artificial Neuron Using Various Activation Functions and XOR Gate on FPGA Chip

Abstract

In this paper, a hardware implementation of an artificial neural network on Field Programmable Gate Arrays (FPGA) is done step by step. First single neurons are implemented using different activation function and then a XOR Gate is implemented. The concurrent structure of a neural network makes it very fast for the computation of certain tasks. This makes ANN well suited for implementation in VLSI technology. Hardware realization of a Neural Network depends on the efficient implementation of Artificial single neuron. FPGA-based reconfigurable computing architectures are suitable for hardware implementation of neural networks. FPGA realization of ANNs with a large number of neurons is still a challenging task. Here design and implementation of a Single neuron with various activation functions is done and then an XOR Gate is implemented using one of these designs. The design of XOR Gate is done by using gradient descent algorithm and taking 3-layers 5-neurons model.