SPICE Simulation Research Articles

Fabrication, compact & device modeling of 4H–21DNTT organic thin film transistor

Abstract In this study, we explored a novel organic semiconductor (OSC), 6,6 bis-(trans4-butylcyclohexyl) dinaphtho[2,1-b:2,1-f]thieno[3,2-b]thiophene (4H–21DNTT). The work also includes a TCAD device model for optimizing and improving the device performance. Both the experimental and simulated results have demonstrated sufficient mobility to realize complex circuits. To validate its potential, a compact model was developed and employed in the SPICE simulator for complex-circuit simulations. Both models accurately capture the below-threshold, linear, and saturation operating conditions through a unified approach, removing the necessity for explicitly defining the threshold and saturation voltages.

A fin-gate p-GaN HEMT with high threshold voltage and improved dynamic performance

A novel fin-gate p-GaN (FPG) HEMT is proposed to simultaneously increase threshold voltage (Vth) and improve dynamic performance of the p-GaN HEMT. The fin-gate structure works as a normally-on p-channel MESFET between gate and source by forming a Schottky-type contact on sidewall and a source-connected Ohmic-type contact on top of the fin. Thus, the Vth can change with the shutdown voltage of the p-channel MESFET, which can be modulated by the doping concentration and width of the fin-p-GaN. By optimizing the fin structure, a high positive Vth of 4V is achieved without transconductance and breakdown voltage degradation in this work. It breaks the restriction between Vth and on-resistance for conventional p-GaN HEMT. The dynamic characteristics of the FPG HEMT are investigated by SPICE simulations. Owing to the well-grounded p-GaN through the normally-on MESFET, the recovery process of the dynamic shift in Vth (ΔVth) after on/off-state stress can be accelerated by two orders of magnitude. It means an imperceptible dynamic degradation and a great potential in high frequency application for the FPG HEMT.

VCII‐Based Immittance Simulators: Generalized Parallel Configurations

ABSTRACTIn this paper, four new generalized configurations of grounded parallel‐type immittance simulators are proposed. These circuits implement parallel resistor–inductor (RL), parallel resistor–capacitor (RC), parallel capacitor–frequency‐dependent negative resistance (CD), and capacitance multiplier configurations utilizing only two second‐generation voltage conveyors (VCII±) as active elements along with three impedances, without the need for specific matching conditions. The applicability of the proposed parallel RL and capacitance multiplier configurations as a second‐order high‐pass filter (HPF) and a first‐order low‐pass filter (LPF), respectively, is also demonstrated. These applications illustrate the versatility and utility of the proposed structures. Frequency, transient, and Monte Carlo analysis utilizing the CMOS VCII± in the SPICE simulation tool have also been performed to validate the feasibility of the presented circuits. Further validation is carried out through layout design in Cadence Virtuoso, employing 0.18‐μm CMOS technology. Both presimulation and postsimulation results are presented for a thorough assessment of the proposed circuits. Also, the claimed theory is verified by experimental results based on the VCII implementation with commercially available IC AD844.

Smart-CX – Method of extraction of parasitic capacitances in ICs

This paper proposes a novel rule-based parasitic capacitance extraction methodology, integrated into Smart-CX, to enhance the accuracy of SPICE simulations and physical verification of ICs. This methodology is crucial during the microchip design phase, particularly in preparation for fabrication on mature to advanced process nodes. The proposed enhanced analytical method addresses the accuracy/time tradeoffs between numerical and analytical extraction techniques. This study validates the accuracy of the methodology by comparison of the extracted parasitic parameters with foundry-provided 2D-models. The parasitic capacitances that are extracted within this method include: area capacitances (Ca), coupling capacitances (Cc), including via-to-via capacitances (Cmv), contact-to-gate capacitances (Cmg), contact-to-active capacitances (Cmc) and fringe type capacitances with the top (Cft) and bottom (Cfb) conductive layers.

Predicting unparalleled degradation progression in PV module using simulation of shunt resistance experimental data

Datasets of various levels of solar cell shunt resistances were available in the literature, resulting in a linear correlation to forecast shunt resistance (Rsh) degradation and failures in photovoltaic (PV) cells. However, some PV failures initiate mildly with one or few cells in a PV module and then distribute to other cells which leads to a major power reduction as well as critical safe operation. Simulating these experimental datasets gives the potential to catch these unparalleled degradations in PV modules at early stages, preventing them from turning critical. In response, SPICE simulation was used to study the effect of PV cells with low shunt resistance in a PV module. The simulation follows four steps, focusing on the electrical output of Current-Voltage (I-V) curve of the solar cells: (a) simulation of the experimental healthy I-V curve of a PV cell; (b) simulation of experimental eleven I-V curves at reduced levels of shunt resistance; (c) simulation of a PV module by using the simulation parameters obtained from the former steps; and (d) lastly, simulation of four different scenarios depending on the number of faulty cells in a PV module. The effect of these scenarios on the I-V curve parameters is compared. Results revealed it is feasible to detect unparalleled degradations, spotting the failed cells (reduced Rsh) in a PV module by implementing a linear model correlating open-circuit voltage (VOC) with short-circuit-current (ISC) (acting as a proxy of Irradiance) at different shunt resistance levels. This model can be simulated as a robust indicator of PV abnormalities and is appropriate for employment in online PV monitoring systems.

A Novel High-Performance Voltage Differencing Buffered Amplifier

In this paper, a novel approach is introduced for the development of a power-efficient voltage differencing buffered amplifier (VDBA) by incorporating an adaptive biasing circuit. The proposed design is specifically tailored to exhibit low power consumption. The VDBA proposed in this study includes a conventional transconductance unit (TU) with an adaptive biasing and a positive feedback circuit. Incorporating adaptive bias cells and cross-coupled positive feedback circuit, the VDBA structure allows for boosted tunable gain based on the input differential voltage. The proposed VDBA shows improved transconductance gain, transient characteristics, linearity for a wide range of inputs, and reduced standby power dissipation. A mathematical formulation has been presented to define the characteristics of the proposed VDBA. To validate the proposed VDBA structure, SPICE simulations were conducted using 180 nm CMOS technology. The input linear range of the proposed VDBA is ± 250 mV. The 3 dB bandwidth of the proposed structure is 200 MHz. The THD has been found low. The Monte Carlo simulations have also been carried out and found the proposed structure is less sensitive to the different parameter variations. The slew rate of the proposed VDBA is found 26.2 V/µS. As an application example, a voltage mode universal MISO biquad filter is also proposed using the proposed structure VDBA.

High-Performance Method and Architecture for Attention Computation in DNN Inference.

In recent years, The combination of Attention mechanism and deep learning has a wide range of applications in the field of medical imaging. However, due to its complex computational processes, existing hardware architectures have high resource consumption or low accuracy, and deploying them efficiently to DNN accelerators is a challenge. This paper proposes an online-programmable Attention hardware architecture based on compute-in-memory (CIM) marco, which reduces the complexity of Attention in hardware and improves integration density, energy efficiency, and calculation accuracy. First, the Attention computation process is decomposed into multiple cascaded combinatorial matrix operations to reduce the complexity of its implementation on the hardware side; second, in order to reduce the influence of the non-ideal characteristics of the hardware, an online-programmable CIM architecture is designed to improve calculation accuracy by dynamically adjusting the weights; and lastly, it is verified that the proposed Attention hardware architecture can be applied for the inference of deep neural networks through Spice simulation. Based on the 100nm CMOS process, compared with the traditional Attention hardware architectures, the integrated density and energy efficiency are increased by at least 91.38 times, and latency and computing efficiency are improved by about 12.5 times.

Analysis of an operational trans-conductance amplifier with positive feedback

In this paper, we present an analysis of an operational trans-conductance amplifier (OTA) with two positive feedback. The direct current (DC) transfer function is obtained by analyzing the OTA using the drain current in the weak inversion region. The analysis results were verified through comparison with SPICE simulations, and the characteristics of the DC transfer function analysis for the OTA design are well matched with the simulation results. The designed OTA dissipates a low power of 41.4 nW, and features the slew rate is improved by 436% compared to a conventional OTA without two positive feedback. Additionally, a DC gain and a unity-gain bandwidth is improved by 36 dB and 6.7 times, respectively. The OTAs are designed for the 0.18 μm complementary metal–oxide–semiconductor (CMOS) process.

A two‐step sizing method for multistage Op Amps based on behavioral initial sizing followed by Spice‐in‐the‐loop refining

AbstractAnalog integrated circuit sizing is a laborious process that requires many times of iteration with Spice simulations. Even by applying the method, it still requires iterations and test assignment of device values (and biasings) in each iteration until reaching a satisfactory sizing result. When facing a design of multiple‐stage circuits (such as multiple‐stage operational amplifier [Op Amp]), sizing becomes more challenging due to the requirement on pole‐zero placement in order to achieve a better high‐frequency performance. Simulation‐in‐the‐loop method has been the dominating means taken by a great many of existing circuit sizer, but they suffer from intolerable runtime while lacking the possibility of offering insight or design knowledge acquisition. On the other hand, behavioral‐level synthesis methods, although intuitive and fast, suffer from accuracy loss due to the adoption of simplified device models and significantly condensed design equations. However, a proper combination of these two types of methods could lead to a lucrative research territory, yet it demands a methodological development for efficient deployment in practice, namely, implementation easy, less runtime, and guaranteed sizing quality. In this paper, we propose a two‐step method that takes the advantage of behavioral synthesis (in the first step) that is capable of fast and broader coverage of design space then makes correction (in the second step) on sizing refining by Spice simulation. Due to the profiling knowledge acquired on the design space in the first step, it can avoid blindness of the optimization landscape that is faced by many simulation‐centric methods which could easily get trapped in local optima. Conducted experiments over eight three‐stage Op Amps with different compensation configurations, including nested Miller capacitor (NMC), NMC with feedforward path (NMCF), NMC with feedforward path and nulling resistor (NMCFNR), NMC with nulling resistor (NMCNR), double pole‐zero cancellation (DPZC), transconductance with capacitances feedback compensation (TCFC), impedance adapting compensation (IAC), active feedback frequency compensation (AFFC), have validated that the proposed method can successfully generate qualified sizing results, offering an opportunity to compare fairly what merit a specific compensation strategy could possibly have.

Gate breakdown induced stuck bits in sub-20 nm FinFET SRAM

This paper discusses the stuck bits induced by the gate breakdown of PMOS in the sub-20 nm FinFET static random access memory (SRAM) device. After the heavy-ion experiment, several stuck bits are in the FinFET SRAM matrix, which cannot be set or reset. To investigate the factors that caused the stuck bit, we perform the electrical failure analysis (EFA) to measure the electric characteristics of the transistors in the stuck bits and normal cells separately. The measurement results show a clear gate breakdown at the PMOS pull-up (PPU) transistor in all of the measured SRAM cells. Meanwhile, the SPICE simulation based on the EFA results verifies the impact of the damaged PPU. Finally, considering all of the phenomena, the charge deposition from single events is the major mechanism that causes the stuck bits in FinFET SRAM. The experiment results alert a potential gate breakdown risk in the ultra-high-density FinFET SRAM applied in the space environment.

Grounded and floating memristor emulator employing ICCTA: decremental or incremental operation

ABSTRACT This article describes floating and grounded memristor emulator built with an Inverting Current Conveyor Transconductance Amplifier (ICCTA). One ICCTA, one capacitor, and three resistors are used to implement the charge controlled floating memristor emulator. In contrast, a flux controlled grounded memristor emulator consists of one ICCTA, one resistor, and one capacitor. Both presented circuits do not incorporate complex circuits such as analog multiplier circuits, passive inductors, and analog to digital converter circuits in their implementation, which is advantageous in terms of circuit realisation. The designed circuits may be operated in incremental as well as decremental configurations by appropriate setting of MOS switches. In addition, PVT (process, voltage, and temperature) analysis of the proposed memristor is also included. Furthermore, the non-ideal explanation of the proposed circuits is mathematically examined. The proposed emulators are simulated in SPICE simulator using 180 nm technology. Meminductor circuit and memristor-based low pass filter are used to validate the effectiveness of the designed circuits.

Piezoelectric Transducers: Complete Electromechanical Model with Parameter Extraction.

This paper presents a complete electromechanical (EM) model of piezoelectric transducers (PTs) independent of high or low coupling assumptions, vibration conditions, and geometry. The PT's spring stiffness is modeled as part of the domain coupling transformer, and the piezoelectric EM coupling coefficient is modeled explicitly as a split inductor transformer. This separates the coupling coefficient from the coefficient used for conversion between mechanical and electrical domains, providing a more insightful understanding of the energy transfers occurring within a PT and allowing for analysis not previously possible. This also illustrates the role the PT's spring plays in EM energy conversion. The model is analyzed and discussed from a circuits and energy harvesting perspective. Coupling between domains and how loading affects coupled energy are examined. Moreover, simple methods for experimentally extracting model parameters, including the coupling coefficient, are provided to empower engineers to quickly and easily integrate PTs in SPICE simulations for the rapid and improved development of PT interface circuits. The model and parameter extractions are validated by comparing them to the measured response of a physical cantilever-style PT excited by regular and irregular vibrations. In most cases, less than a 5-10% error between measured and simulated responses is observed.

An aging simulation method based on the change of input vector inside the critical path

Abstract With the large-scale expansion and process shrinking of modern integrated circuits, aging has become one of the main factors threatening circuit reliability. To evaluate the impact of aging on circuit life, it is important to investigate aging simulation methods. Aiming at the problem of slow speed and insufficient accuracy of large-scale digital circuit aging simulation methods, a circuit aging simulation method based on the change of input vector inside the critical path (CICP) is proposed in this paper. First, the critical path (CP) with the tightest timing is extracted by static timing analysis (STA), and SPICE simulation is carried out to accurately predict the aging of the CP of the circuit. Second, the aging simulation is carried out considering the change of the internal input vector of the CP. The simulation results show that after changing the internal input signal, the aging path delay increases up to 3.5%.

SPICE Modelling-Assisted evaluation of dynamic on-resistance characterization in Schottky p-GaN HEMTs amid synchronous buck transient instabilities

This study addresses the critical gap in dynamic on-resistance characterization for GaN HEMTs within the initial unstable state in a non-isolated DC-DC converter, where the output voltage and currents fluctuate and exhibit overshoots or undershoots before stabilizing to their steady-state values, a domain within solar photovoltaic (PV) Maximum Power Point Tracking (MPPT) implementations which is crucial yet insufficiently examined. The authors present a novel multi-pulse test circuit within a synchronous buck converter configuration, complemented by SPICE simulation. This combination allows for the accurate assessment of clamping circuits' performance during transient states, significantly improving the precision of RDS(ON) measurements in unsteady phases. The approach deviates from conventional methods by merging empirical data with simulation insights to validate the efficacy of clamping circuits. The experimental results affirm the methodology's precision, with the highlighted Circuit V showcasing a marginal deviation of 2.32 % from existing benchmarks. This finding substantiates the method's dependability and practicality contributing to the GaN power electronics field. In addition, this research provides a powerful analytical tool for RDS(ON) evaluation, culminating in the design of a test PCB that synergizes with both simulated and empirical evidence, contributing future research in GaN HEMT power converter applications.

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

As AI models grow in complexity to enhance accuracy, supporting hardware encounters challenges such as heightened power consumption and diminished processing speed due to high throughput demands. Compute-in-memory (CIM) technology emerges as a promising solution. Furthermore, carbon nanotube field-effect transistors (CNFETs) show significant potential in bolstering CIM technology. Despite advancements in silicon semiconductor technology, CNFETs pose as formidable competitors, offering advantages in reliability, performance, and power efficiency. This is particularly pertinent given the ongoing challenges posed by the reduction in silicon feature size. We proposed an ultra-low-power architecture leveraging CNFETs for Binary Neural Networks (BNNs), featuring an advanced state-of-the-art 8T SRAM bit cell and CNFET model to optimize performance in intricate AI computations. Through meticulous optimization, we fine-tune the CNFET model by adjusting tube counts and chiral vectors, as well as optimizing transistor ratios for SRAM transistors and nanotube diameters. SPICE simulation in 32 nm CNFET technology facilitates the determination of optimal transistor ratios and chiral vectors across various nanotube diameters under a 0.9 V supply voltage. Comparative analysis with conventional FinFET-based CIM structures underscores the superior performance of our CNFET SRAM-based CIM design, boasting a 99% reduction in power consumption and a 91.2% decrease in delay compared to state-of-the-art designs.

A Simple Thermal Model for Junction and Hot Spot Temperature Estimation of 650 V GaN HEMT during Short Circuit

Temperature is a critical parameter for the GaN HEMT as it sharply impacts the electrical characteristics of the device more than for SiC or Si MOSFETs. Either when designing a power converter or testing a device for reliability and robustness characterizations, it is essential to estimate the junction temperature of the device. For this aim, manufacturers provide compact models to simulate the device in SPICE-based simulators. These models provide the junction temperature, which is considered uniform along the channel. We demonstrate through two-dimensional numerical simulations that this approach is not suitable when the device undergoes high electrothermal stress, such as during short circuit (SC), when the temperature distribution along the channel is strongly not uniform. Based on numerical simulations and experimental measurements on a 650 V/4 A GaN HEMT, we derived a thermal network suitable for SPICE simulations to correctly compute the junction temperature and the SC current, even if not providing information about the possible failure of the device due to the formation of a local hot spot. For this reason, we used a second thermal network to estimate the maximum temperature reached inside the device, whose results are in good agreement with the experimental observed failures.

Estimation of bandwidth, voltage swing and DC coefficients for VLSI interconnects: current mode technique

ABSTRACT Necessity of bandwidth requires the effective use of it for high speed data transmission and faster read/write operation in memory cells. In this paper the transfer function expressions for RC interconnect line is presented for resistive load. The line delay, bandwidth and step response for current and voltage mode signalling is formulated. The current mode and voltage mode signalling provides the 3-dB bandwidth of 6.8 GHz and 3.1 GHz, respectively. An interconnect line modelled as either RLC or RC line depending upon input signal rise time, damping, and range of interconnect length with significant inductance effect is investigated for global interconnect lines. Low swing for column bit line in memory architectures is very important and estimated in terms of dc coefficients. For RC global interconnect of 10 mm, a swing of 0.382 V is obtained for current mode signalling, when a power supply of 1.8 V is applied to the network. DC coefficient and steady state value has been obtained which is significant for power computation on column bit line. It is also analytically validated by SPICE and MATLAB simulations.

P‐54: XAI Models for Efficient Analysis of Temperature and Power Consumption in High‐Brightness Panels and Modules

Predicting temperature and power consumption in panels and modules under high brightness has long been a daunting and time‐intensive task, often requiring over a week of simulation work. Addressing this challenge, our study introduces a novel machine learning framework, bifurcated into panel and module stages, to streamline the data acquisition process. A key innovation in our approach is the use of symbolic regression to overcome the limitations posed by the reliance on real‐world measurements for power consumption and heat generation. Employing SPICE simulations, we estimated the current density within the panel, with subsequent validation through Explainable AI (XAI) analysis. This revealed a significant correlation between current density and panel heat generation. Our research also revisits the traditionally neglected areas outside the panel's center, uncovering their impact on heat generation. The layered complexity in modules, previously a barrier to physical sample creation and measurement, was navigated using simulation. XAI insights demonstrated the crucial roles of graphite and metal layers in heat dissipation, and the drive IC as a primary heat source. This integrated approach of real and computational data in machine learning significantly reduced the analysis timeframe from a week to mere minutes, marking a breakthrough in predictive accuracy and efficiency for high‐brightness scenarios.

Sampling the user controls in neural modeling of audio devices

This work studies neural modeling of nonlinear parametric audio circuits, focusing on how the diversity of settings of the target device user controls seen during training affects network generalization. To study the problem, a large corpus of training datasets is synthetically generated using SPICE simulations of two distinct devices, an analog equalizer and an analog distortion pedal. A proven recurrent neural network architecture is trained using each dataset. The difference in the datasets is in the sampling resolution of the device user controls and in their overall size. Based on objective and subjective evaluation of the trained models, a sampling resolution of five for the device parameters is found to be sufficient to capture the behavior of the target systems for the types of devices considered during the study. This result is desirable, since a dense sampling grid can be impractical to realize in the general case when no automated way of setting the device parameters is available, while collecting large amounts of data using a sparse grid only incurs small additional costs. Thus, the result provides guidance for efficient collection of training data for neural modeling of other similar audio devices.

Development of a Flexible Sensor-Integrated Tissue Patch to Monitor Early Organ Rejection Processes Using Impedance Spectroscopy.

Heart failure represents a primary cause of hospitalization and mortality in both developed and developing countries, often necessitating heart transplantation as the only viable recovery path. Despite advances in transplantation medicine, organ rejection remains a significant post-operative challenge, traditionally monitored through invasive endomyocardial biopsies (EMB). This study introduces a rapid prototyping approach to organ rejection monitoring via a sensor-integrated flexible patch, employing electrical impedance spectroscopy (EIS) for the non-invasive, continuous assessment of resistive and capacitive changes indicative of tissue rejection processes. Utilizing titanium-dioxide-coated electrodes for contactless impedance sensing, this method aims to mitigate the limitations associated with EMB, including procedural risks and the psychological burden on patients. The biosensor's design features, including electrode passivation and three-dimensional microelectrode protrusions, facilitate effective monitoring of cardiac rejection by aligning with the heart's curvature and responding to muscle contractions. Evaluation of sensor performance utilized SPICE simulations, scanning electron microscopy, and cyclic voltammetry, alongside experimental validation using chicken heart tissue to simulate healthy and rejected states. The study highlights the potential of EIS in reducing the need for invasive biopsy procedures and offering a promising avenue for early detection and monitoring of organ rejection, with implications for patient care and healthcare resource utilization.