Spartan-6 Field Programmable Gate Array Research Articles

State Space Modeling and Implementation of a New Transformer Based Multilevel Inverter Topology with Reduced Switch Count

This paper presents a new transformer based multilevel inverter, with a novel pulse width modulation scheme to achieve seven-level inverter output voltage. The proposed inverter switching pattern consists of three fundamental frequency sinusoidal reference signals with an offset value, and one high frequency triangular carrier signal. This switching scheme has been implemented using an 8-bit Xilinx SPARTAN-3E field programmable gate array based controller. In addition, the state space model of the proposed inverter is developed. The significant features of the proposed topology are: reduction of the power switch count and the gate drive power supply unit, the provision of a galvanic isolation between load and sources by a centre tap transformer. An exhaustive comparison has been made of the existing multilevel inverter topologies and the proposed topology. The performances of the proposed topology with resistive, resistive-inductive loads are simulated in a MATLAB environment and validated experimentally on a laboratory prototype.

FPGA-Based High-Frequency Digital Pulse Width Modulator Architecture for DC-DC Converters

Digital pulse width modulator is an integral part in digitally controlled Direct Current to Direct Current (DC-DC) converter utilized in modern portable devices. This paper presents a new Digital Pulse Width Modulator (DPWM) architecture for DC-DC converter using mealy finite state machine with gray code encoding scheme and one hot encoding method to derive the variable duty cycle Pulse Width Modulation (PWM) signal without varying the clock frequency. To verify the proposed DPWM technique, the architecture with control input of six, five and four bits are implemented and the maximum operating frequency along with power consumption results is obtained for different Field Programmable Gate Array (FPGA) devices. The post layout timing results are presented showing that architecture can work with maximum frequency of 326 MHz and derive PWM signal of 3.59 MHz. Experimental results show the implementation of the proposed architecture in low-cost FPGA (Spartan 3A) with on-board oscillator clock frequency of 12 MHz which is multiplied internally by two with Digital Clock Manager (DCM) and derive the PWM signal of 1.5 MHz with a time resolution of 1 ps.

VLSI Implementation of Area-Efficient and Low Power OFDM Transmitter and Receiver

Background: This paper consists of an analysis of Fast Fourier Transform (FFT) architectures which are the backbone of any OFDM based wireless networks. Methods: By using the FFT concepts we are indeed in developing an efficient architectures for wireless networks which are common in everywhere now-a-days, Our concepts are purely based upon in development we have to test it by using Field Programmable Gate Array (FPGA),we are using Xilinx based Spartan-3e FPGA. Results: The concepts are simulated by using Modelsim6.3c and to synthesize by using Xilinx ISE 10.1.

Long-range vibration detection system using heterodyne interferometry.

We present the design and performance of an extremely sensitive coherent remote vibration detection system using optical heterodyne vibration of phase shifts produced by laser light scattered off a remote target. The resulting phase-modulated intermediate RF of 200MHz, which carries the vibrational motion of the target, is demodulated down to baseband using an RF in-phase and quadrature demodulator. Acquisition and calculation of the target phase angle is carried out on a custom-made control board which utilizes high-resolution A/D converters, variable gain amplifiers, and a Spartan-6 field programmable gate array.

Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines.

Cascade support vector machines (SVMs) are optimized to efficiently handle problems, where the majority of the data belong to one of the two classes, such as image object classification, and hence can provide speedups over monolithic (single) SVM classifiers. However, SVM classification is a computationally demanding task and existing hardware architectures for SVMs only consider monolithic classifiers. This paper proposes the acceleration of cascade SVMs through a hybrid processing hardware architecture optimized for the cascade SVM classification flow, accompanied by a method to reduce the required hardware resources for its implementation, and a method to improve the classification speed utilizing cascade information to further discard data samples. The proposed SVM cascade architecture is implemented on a Spartan-6 field-programmable gate array (FPGA) platform and evaluated for object detection on 800×600 (Super Video Graphics Array) resolution images. The proposed architecture, boosted by a neural network that processes cascade information, achieves a real-time processing rate of 40 frames/s for the benchmark face detection application. Furthermore, the hardware-reduction method results in the utilization of 25% less FPGA custom-logic resources and 20% peak power reduction compared with a baseline implementation.

Reliable Radix-4 Complex Division for Fault-Sensitive Applications

Complex division is commonly used in various applications in signal processing and control theory including astronomy and nonlinear RF measurements. Nevertheless, unless reliability and assurance are embedded into the architectures of such structures, the sub-optimal (and thus erroneous) results could undermine the objectives of such applications. As such, in this paper, we present schemes to provide complex number division architectures based on Sweeney, Robertson, and Tocher-division with error detection mechanisms. Different error detection architectures are proposed in this paper which can be tailored based on the eventual objectives of the designs in terms of area and time requirements, among which we pinpoint carefully the schemes based on recomputing with shifted operands to be able to detect faults based on recomputations for different operands in addition to the unified parity (simplified detecting code) and hardware redundancy approach. The design also implements a minimized look up table approach which favors in error detection based designs and provides high fault coverage with relatively-low overhead. Additionally, to benchmark the effectiveness of the proposed schemes, extensive error detection assessments are performed for the proposed designs through fault simulations and field-programmable gate array (FPGA) implementations; the design is implemented on Xilinx Spartan-6 and Xilinx Virtex-6 FPGA families.

Wide dynamic range FPGA-based TDC for monitoring a trigger timing distribution system in linear accelerators

A new field-programmable gate array (FPGA)-based time-to-digital converter (TDC) with a wide dynamic range greater than 20ms has been developed to monitor the timing of various pulsed devices in the trigger timing distribution system of the KEKB injector linac for the Super KEK B-factory project. The pulsed devices are driven by feeding regular as well as any irregular (or event-based) timing pulses. The timing pulses are distributed to these pulsed devices along the linac beam line with fiber-optic links on the basis of the parameters to be set pulse-by-pulse in the event-based timing and control system within 20ms. For monitoring the timing as precisely as possible, a 16-ch FPGA-based TDC has been developed on a Xilinx Spartan-6 FPGA equipped on VME board with a resolution of 1ns. The resolution was achieved by applying a multisampling technique, and the accuracies were 2.6ns (rms) and less than 1ns (rms) within the dynamic ranges of 20ms and 7.5ms, respectively. The various nonlinear effects were improved by implementing a high-precision external clock with a built-in temperature-compensated crystal oscillator.

Implementation of Audio Effect Generator in FPGA

This paper describes the theory and implementation of audio effects such as echo, distortion and pitch-shift in Field Programmable Gate Array (FPGA). At first the mathematical formulation for generation of such effects is explained and then the algorithm is described for its implementation in FPGA using Very high speed integrated circuit hardware descriptive language (VHDL). The digital system being designed, which is synthesizable and reconfigurable, offers a great flexibility and scalability in designing and prototyping in FPGAs. The system is divided into three HDL blocks, each for echo, distortion, and pitch-shift effect generation, which are multiplexed in order to share the common ADC and DAC. The audio effect generator designed in this paper was successfully implemented in Spartan-3E FPGA utilizing the resources available effectively. There has been tremendous research being carried out in the field of IP core. Efficient IP cores designed to carry out digital signal processing are implemented in every modern device using configurable logics. This trend hasn’t yet been realized in Nepal. Through the design and implementation of audio effect generator, this paper also aims at bringing the field of IP core development to limelight among scholars of Nepal.DOI: http://dx.doi.org/10.3126/njst.v15i1.12022 Nepal Journal of Science and TechnologyVol. 15, No.1 (2014) 89-98

Design and Implementation of Low-Pass, High-Pass and Band-Pass Finite Impulse Response (FIR) Filters Using FPGA

This paper presents the design and implementation of a low-pass, high-pass and a hand-pass Finite Impulse Response (FIR) Filter using SPARTAN-6 Field Programmable Gate Array (FPGA) device. The filter performance is tested using Filter Design and Analysis (FDA) and FIR tools from Mathworks. The FDA Tool is used to define the filter order and coefficients, and the FIR tool is used for Simulink simulation. The FPGA implementation is carried out using Spartan-6 LX75T-3FGG676C for different filter specifications and simulated with the help of Xilinx ISE (Integrated Software Environment). System Generator ISE design suit 14.6i is used in synthesizing and co-simulation for FPGA filter output verification. Finally, comparison is done between the results obtained from the software simulations and those from FPGA using hardware co-simulation. The simulation waveforms and synthesis reports verify the parallel implementation of FPGA which proves its effectiveness in terms of speed, resource usage and power consumption.

Design of a DPSK Modem Using CORDIC Algorithm and Its FPGA Implementation

ABSTRACTIn the present work, a power efficient differential phase shift keying (DPSK) modem has been implemented using COordinate Rotation DIgital Computer (CORDIC) algorithm in hardware descriptive language (VHDL) code. Here, CORDIC algorithms are used to generate the carrier in the modulator and to implement the multiplier in the demodulator. Carrier generator on the same chip minimizes the effect of noise significantly. Single-chip implementation provides a low power DPSK modem operating with high frequency which is suitable for wireless communication system. The CORDIC algorithm based DPSK modem is found to be a much efficient system in terms of reduced hardware cost, improved performance, and included flexibility. Importance of portable field programmable gate array (FPGA) based device for wireless communication system and system on single chip is now growing rapidly. In this context, the proposed modem provides an efficient alternative over conventional DPSK modem. Real-time verification is performed using Kintex-7 FPGA board. The performance of the proposed modem has been compared with a normal DPSK modem implemented in software defined radio kit using Xilinx block and Spartan-6 FPGA.

Efficient Digital Implementation of Signal Processing Algorithms in State-Of-The-Art Field-Programmable Gate Arrays for Gamma-Ray Spectroscopy

In this work, a board based on a Spartan-3 field-programmable gate array was designed as a hardware prototyping platform for development of a multichannel digital gamma spectrometer. The device is compatible with various detectors like high-purity germanium, NaI, and CsI detectors. Before implementing the hardware, the method for digital signal processing for gamma spectroscopy was developed. The aim of this paper is to introduce a robust tool suitable for optimizing the design of complicated systems. The characteristics of this method, such as its ability to implement adaptive shaping, are investigated. The optimum conditions for digital filtering were determined using MATLAB/Simulink. This scheme can be useful for commercial production. Simulation was used to examine each processing unit in the whole signal processing procedure including cusplike shaping. The proposed method can be used as a computer design tool for optimizing digital multichannel analyzers or digital nuclear spectrometers.

Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control

This paper presents an improved adaptive fuzzy logic speed controller for a DC motor, based on field programmable gate array (FPGA) hardware implementation. The developed controller includes an adaptive fuzzy logic control (AFLC) algorithm, which is designed and verified with a nonlinear model of DC motor. Then, it has been synthesised, functionally verified and implemented using Xilinx Integrated Software Environment (ISE) and Spartan-3E FPGA. The performance of this controller has been successfully validated with good tracking results under different operating conditions.

REALIZATION OF HIGH PERFORMANCE RUN-TIME LOADABLE MIPS SOFT-CORE PROCESSOR

Soft-core processors on Field Programmable Gate Array (FPGA) chips are becoming a solution for application-specific customization. Soft-core processors provide several advantages for designer. Currently using microprocessor doesn’t support realtime loading. If, any change in the assembly code of the implemented processor, it requires re-implementation and downloads the softcore on FPGA. This project proposes realization of run-time loading technique of a MIPS (Microprocessor without Interlocked Pipeline Stages) soft- core processor on FPGA. The proposed system consists of mainly three components: microprocessor soft-core, software tool and universal asynchronous Receiver/Transmitter (UART). Since, here MIPS code is updating instantly there is no need of resynthesize, place, route, and reload the soft-core. The software tool communicates between the user and MIPS soft-core processor through UART. Five stage pipelining is included to improve the overall processor performance. In this paper 32-bit MIPS soft-core processor, RAM module, APB Interface is designed and simulated using Modelsim. Design architecture will be doing in Verilog, simulate using Modelsim 10.3 simulator and realize in Spartan-6 FPGA using Xilinx ISE 14.2.

Synchronization in coupled Ikeda delay systems

In this work, we demonstrate the use of a Field Programmable Gate Array (FPGA) as a physical platform for realizing chaotic delay differential equations (DDE). Moreover, using our platform, we also experimentally study the synchronization between two time delayed systems. We illustrate two different experimental approaches – one is hardware co-simulation (using a Digilent Atlys with a Xilinx Spartan-6 FPGA) and the other is analog output (using a Terasic DE2-115 with an Altera Cyclone IV E FPGA).

All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator

This brief presents a simple all-digital variable-length ring oscillator (VLRO) design that is capable of synchronously changing the output frequency while keeping a signal free of glitches or spurious oscillations at the frequency transitions. The correct operation of the proposed VLRO has been experimentally validated on a 90-nm Xilinx Spartan-3E field-programmable gate array, showing the ability to switch between 16 different frequencies (from 24.1 to 321 MHz for the nominal core supply voltage) under different supply voltages with the expected behavior.

Two‐stage logarithmic converter with reduced memory requirements

This study presents an efficient method for converting a normalised binary number x (1 ≤ x <; 2) into a binary logarithm. The algorithm requires less memory and fewer arithmetic components to achieve 23 bits of fractional precision than other algorithms using uniform and non-uniform piecewise linear or piecewise polynomial techniques and requires less than 20 kbits of ROM and a maximum of three multipliers. It is easily extensible to higher numeric precision and has been implemented on Xilinx Spartan3 and Spartan6 field programmable gate arrays (FPGA) to show the effect of recent architectural enhancements to the reconfigurable fabric on implementation efficiency. Synthesis results confirm that the algorithm operates at a frequency of 42.3 MHz on a Spartan3 device and 127.8 MHz on a Spartan6 with a latency of two clocks. This increases to 71.4 and 160 MHz, respectively, when the latency is increased to eight clocks. On a Spartan6 XC6SLX16 device, the converter uses just 55 logic slices, three multipliers and 11.3kbits of Block RAM configured as ROM.

Implementation of AES on FPGA

Advanced Encryption Standard (AES) a National Institute of Standards and Technology specification is an approved cryptographic algorithm that can be used for securing electronic data. Reprogrammable devices such as Field Programmable Gate Arrays (FPGA) are highly attractive option for hardware implementations of cryptographic algorithm AES as they offer a quicker and more customizable solution. This paper proposes an efficient FPGA implementation of advanced encryption standard (AES). We implement the AES encryption algorithm on Xilinx Spartan-3 FPGA and decryption is done on PC. The coding for encryption is done in VHDL language and for decryption in Visual Basic. To implement AES Rijndael algorithm on FPGA plain text of 128 bit data is considered. Advanced Encryption Standard (AES) RIJNDAEL on FPGA offers a better performance than any other cryptographic algorithms.

FPGA based Smart Wireless MIMO Control System

In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input & Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively.

Embedded system based on a real time fuzzy motor speed controller

This paper describes an implementation of a fuzzy logic control (FLC) system and a/the conventional proportional-integral (PI) controller for speed control of DC motor, based on field programmable gate array (FPGA) circuit. The proposed scheme is aimed to improve the tracking performance and to eliminate the load disturbance in the speed control of DC motors. The proposed fuzzy system has been applied to a permanent magnet DC motor, via a configuration of H-bridge. The fuzzy control algorithm is designed and verified with a nonlinear model, using the MATLAB® tools. Both FLC and conventional PI controller hardware are synthesized, functionally verified and implemented using Xilinx Integrated Software Environment (ISE) Version 11.1i. The real time implementation of these controllers is made on Spartan-3E FPGA starter kit (XC3S500E). The practical results showed that the proposed FLC scheme has better tracking performance than the conventional PI controller for the speed control of DC motors.

Designing a Four-by-Four Keypad Arbitrary-Key-Entry Detector

This paper presents a field programmable gate array (FPGA) prototype of a four-by-four keypad arbitrary-key-entry detector design for entering any arbitrary set of the 4x4 keypad keys. The number of the valid keys was defined by a multiple-bit mask input. The character code of the prohibited key would not be generated after a key stroke. A valid-key stroke caused the detector circuit to generate a 4-bit hexadecimal character code and a sampling tick for the next-stage device to capture the pressed key information. The detector design and the testing circuitry were implemented on an Atlys Spartan-6 FPGA Development Board. The design itself can be incorporated into a wide variety of key-entry tools on electronic instruments, mechanical devices, medical apparatus, and more, to improve the key-stroke filtering and ease the interface connection.