Spare Elements Research Articles

Real Time Reliability Study of a Model with Increasing Failure Rates

This paper deals with a system with elements with one element is the main element and the other elements are the spare parts of the main element. If one element fails, one of the spare parts starts working immediately. The failure rate of non working elements are zero and the failure rate of working element is time dependent as and the failed elements are not repairable. The system works until all elements failed. In the second part of this paper the differential equations between the state of the system are established and by solving this equation the reliability function of the system () is calculated. In the third part, a numerical example solved to determine the parameters of the system. Nomenclature The notations used in this paper are as follows: : Number of elements, : Failure rate of each element at time, : Probability that the system is in state with spare element at time, : Probability that system works at time, : Mean time to failure of the system,

A Memory Built-In Self-Repair Scheme Based on Configurable Spares

There is growing need for embedded memory built-in self-repair (MBISR) due to the introduction of more and more system-on-chip (SoC) and other highly integrated products, for which the chip yield is being dominated by the yield of on-chip memories, and repairing embedded memories by conventional off-chip schemes is expensive. Therefore, we propose an MBISR generator called BRAINS+, which automatically generates register transfer level MBISR circuits for SoC designers. The MBISR circuit is based on a redundancy analysis (RA) algorithm that enhances the essential spare pivoting algorithm, with a more flexible spare architecture, which can configure the same spare to a row, a column, or a rectangle to fit failure patterns more efficiently. The proposed MBISR circuit is small, and it supports at-speed test without timing-penalty during normal operation, e.g., with a typical 0.13 μm complementary metal-oxide-semiconductor technology, it can run at 333 MHz for a 512 Kb memory with four spare elements (rows and/or columns), and the MBISR area overhead is only 0.36%. With its low area overhead and zero test-time penalty, the MBISR can easily be applied to multiple memories with a distributed RA scheme. Compared with recent studies, the proposed scheme is better in not only test-time but also area overhead.

Chip Self-Organization and Fault Tolerance in Massively Defective Multicore Arrays

We study chip self-organization and fault tolerance at the architectural level to improve dependable continuous operation of multicore arrays in massively defective nanotechnologies. Architectural self-organization results from the conjunction of self-diagnosis and self-disconnection mechanisms (to identify and isolate most permanently faulty or inaccessible cores and routers), plus self-discovery of routes to maintain the communication in the array. In the methodology presented in this work, chip self-diagnosis is performed in three steps, following an ascending order of complexity: interconnects are tested first, then routers through mutual test, and cores in the last step. The mutual testing of routers is especially important as faulty routers are disconnected by good ones with no assumption on the behavior of defective elements. Moreover, the disconnection of faulty routers is not physical (“hard”) but logical (“soft”) in that a good router simply stops communicating with any adjacent router diagnosed as defective. There is no physical reconfiguration in the chip and no need for spare elements. Ultimately, the multicore array may be viewed as a black box, which incorporates protection mechanisms and self-organizes, while the external control reduces to a simple chip validation test which, in the simplest cases, reduces to counting the number of valid and accessible cores.

Approximation algorithm for evaluating time-to-failure distribution of k-out-of- n system with shared standby elements

The paper presents an approximation algorithm for evaluating cdf of time-to-failure for k-out-of- n systems with shared spare elements. The working and spare elements can have different arbitrary distributions of time-to-failure. Different spare elements can be in different standby modes: cold, hot and warm. The algorithm is based on a universal generating function approach. It is shown that for small k the algorithm outperforms simulation.

Optimization of amount of spare elements for aircraft equipment articles

A two-objective problem of optimizing the amount of spare elements for aircraft equipment articles with instantaneous restoration of their efficiency. We present examples of determining the optimal amount of replaceable elements of a workstation for an unmanned aerial vehicle operator.

AVALIAÇÃO DO MANGANÊS EM ACIARIA A OXIGÊNIO

The increasing customer demands of steel quality and requirement of a constant improvement of productivity and competitive steelmaking plant provide the automation operation, due to require the systematic studies of chemistry elements behavior during blowing process. Manganese is the chemical element to which steelmakers have less attention and it is often considered only a spare element. However the manganese has a great influence in the slag formation at the beginning of the process with ascendance in the evolution of slag chemistry composition, refractory erosion and lime dissolution. Additionally the end blow manganese defines the manganese alloy addition to the ladle. The paper evaluates studies and experiences of the manganese behavior in BOF process and describes the CST operation conditions with manganese results in converter operation.

Gestion de l'approvisionnement initial en éléments de rechange d'un système orbital

This article presents a method of management of the initial supply spare parts. This generic problem is of a particular interest in certain systems whose difficulty of accessibility or lifespan constitutes risks related to possible stock of spare elements running out. We consider in this paper the space framework. After having commented on the characteristics of the management of the supplies elements of replacement of an orbiting station, we propose a method based on minimization of the risk of carry out of a maintenance action. An application to the Columbus laboratory of the International Space Station is finally presented.

MODEL OF SYSTEM AVAILABILITY CAUSED BY SPARE PARTS INVENTORY LEVEL

There are many models and methods that enable estimation system availability when set size of spares inventory is accessible. Correct determining of standby of a system should consider also the lack of inventory delivery precision effect. The paper presents model of inventory critical level of spare element impact on technical system availability when delivery moment is assumed to be a random. Presented approach allows to calculate the probability of the system down time and probability of its availability-based consequences.

Fault tolerant solid state mass memory for space applications

In this paper, an innovative fault tolerant solid state mass memory (FTSSMM) architecture is described. Solid state mass memories (SSMMs) are particularly suitable for space applications and more in general for harsh environments such us, for example, nuclear accelerators or avionics. The presented FTSSMM design has been entirely based on commercial off the shelf (COTS) components. In fact, cost competitive and very high performance SSMMs cannot be easily implemented by using space qualified components, due the technological gap and very high cost characterizing these components. In order to match the severe reliability requirements of space applications a COTS-based apparatus must be designed by using suitable system level methodologies (Kluth, 1996 and Fichna, 1998). In the proposed architecture, error-correcting codes are used to strengthen the commercial dynamic random access memory (DRAM) chips, while the system controller has been designed by applying suitable fault tolerant design techniques. Different from other proposed solutions, our architecture fully exploits the reconfiguration capabilities of Reed-Solomon (RS) codes, discriminates between permanent and transient faults reducing the use of spare elements, and provides dynamic reconfiguration and graceful degradation capability, i.e., the FTSSMM performances are gracefully reduced in case of permanent faults, maintaining part of the system functionality. The paper shows the FTSSMM design methodology, the architecture, the reliability analysis, some simulation results, and a description of its implementation based on fast prototyping techniques.

Failure Analysis on a De-NOx Catalyst of a Large Waste Burner

Modern waste burners are equipped with catalysts to reduce NOX. During operation the catalysts and their performance are influenced by, for example rapid temperature changes, facility vibrations, cleaning procedures and unwashed exhaust gas (when the catalyst is installed before the washer). The catalyst discussed in this paper comprised over 2’500 extruded elements of 150 x 150 x 770 mm3. During commissioning the catalyst elements exhibited a tendency to spall off pieces, thus preventing acceptance of the plant. For the failure analysis, one element from the catalyst was removed and two spare elements were selected. The investigation comprised a visual check, fractography, measurement of the most important physical, mechanical and chemical properties, and a microstructural analysis. It could be shown that: − Processing defects, such as extrusion defects, were the source of cracks which led to pieces spalling off; − Hot steam, used for periodic cleaning, reduced the structural strength by half; − The elements were exposed to higher mechanical loads than expected during transport; − The cleaning process, in combination with particles transported by the exhaust gas, has an erosive effect on the catalyst material; − Blockages, caused by catalyst material among other things, could be found at different depths; − The chemical composition did not significantly differ between used and unused elements. In summary, the failure analysis led to an understanding of the failure mechanism and to a set of recommendations for improvements whose implementation ultimately led to the plant being cleared for operation.

Restructuring of square processor arrays by built-in self-repair circuit

The authors introduce two types of neural networks that can be integrated into array-type very-large-scale integration/wafer-scale integration (VLSI/WSI) chips, allowing them to restructure themselves automatically so that, in the presence of multiple random faults, the array circuits can perform their computations correctly. In the first implementation, the neural network is interconnected and programmed so that it can execute a maximum matching algorithm and thereby substitute appropriate fault-free spare elements for the faulty components. The second implementation rearranges the surviving fault-free processors to restore the logical structure, and it can adjust its interconnection complexity based on the quality of solution (i.e., performance) desired. These two approaches are compared with the traditional reconfiguration algorithms, and by simulation it is shown that the neural network techniques provide superior performance (i.e., higher survivability rates). It is also shown that the intrinsic fault-tolerant nature of neural networks provides a degradable reconfiguration control even in the presence of faulty neural network components. >

A reconfigurable boolean n-cube architecture under faults

A reconfigurable modular Boolean n-cube (RMB n) is proposed in this paper. We embed spare elements, including nodes (processors), switches and links, into each module in order to reconfigure a failed system. The proposed scheme is constructed in two levels. The first level is to build a fault-tolerant module (FTM), using an original 4-cube of 16 nodes with 4 spare nodes and some switches with links. Then, in the second level, we use several FTMs to construct the desired RMB n, n ≥ 4, via connecting the corresponding nodes between any two adjacent FTMs. In our scheme, each spare node can replace any faulty node in the FTM via rebuilding the interconnections, i.e., each FTM can tolerate 4 faulty nodes. A reconfiguration algorithm is developed to choose an adequate spare node such that a faulty node can be replaced. We also develop a distributed routing algorithm to route messages from any source node to any destination node around the faulty nodes. Finally, the RMB n is evaluated and compared with previous works. It is shown that the proposed scheme can achieve the same or higher reliability while using fewer hardware costs.

Predicting performability of a fault-tolerant microcomputer for process control

The performability of a gracefully degrading process-control microcomputer is evaluated. Two Markov models, fault/error handling and fault occurrence and repair, are used to describe the microcomputer. They are solved separately using the behavioral decomposition/aggregation method. A numerical algorithm, based on Laplace and Laplace-Stieltjes transforms, it used to derive system performability. The influence of the permanent, intermittent, and transient faults underline the importance of the detection, isolation, and reconfiguration mechanisms. The effect of the parallelization algorithms is analyzed. The performability increases appreciably when global repair actions are undertaken. Local repair also has a beneficial influence, but only for large amount of required work. Adding spare processing elements improves performability. Their influence becomes visible for large amounts of work. >

Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond

An optimized redundancy scheme for 64-Mb dynamic RAM (DRAM) and beyond that is based on a failure-related yield model is described. This model accounts for three-dimensional memory cell structures and individual design rules used in individual sections of the chip. Failure-mode parameters for the model are determined by performing a trial fuse-blowing test on 4-Mb DRAMs. The test employs a memory tester without requiring complicated visual inspections. The dependence of the yield on block division and the number of spare elements for a 64-Mb DRAM are investigated. In the estimation as a redundancy scheme for the 64-Mb DRAM, more than two spare rows and two spare columns in 1-Mb or less subblocks are shown to be necessary.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

4722084 Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits

An array reconfiguration apparatus is employed in large integrated circuits and large systems. The apparatus makes use of spare wires and/or computation elements which are incorporated in the array. The apparatus uses spare wires in place of defective wires and/or the apparatus uses spare computation elements in place of defective computation elements so that an operational system may be created in spite of the occurrence of numerous manufacturing or lifetime faults. The excess wires are utilized as data input and output lines and as such each data line is associated with a bidirectional buffer/receiver (B/R). The bidirectional B/R's are capable of transmitting data in either direction as from an input terminal to an output terminal or vice versa. Each data line is connected to a bidirectional multiplexing device which has a control input. Control logic means has dynamically stored therein the assignment of each significant wire and each computation element. Only unreliable wires as between integrated circuits are switchable. The control logic selects operational elements as well as operational data lines and hence uses the spare data lines to make connections between the redundant elements on the circuit board so that an array configuration can be implemented in spite of multiple defects on the overall circuit board. The invention further discloses a simple method for computing the assignments of cells and wires to avoid the defects.

A fast 8K × 8 mixed CMOS static RAM

This paper describes a fast 8K × 8 static RAM fabricated with a mixed CMOS technology. To realize a fast access time and yet a low active power, a block-oriented die architecture with four submodules and a new sense amplifier are applied. An address access time of 34 ns and a chip select access time of 38 ns have been achieved at an active power of 90 mW. In addition to redundant memory cells, the RAM incorporates a spare element disable (SED) function to make it easy to obtain the information of the replaced memory cell. Another feature is a high latchup immunity of the CMOS peripheral circuits. This is obtained from an optimized well structure and guard bands around the wells. A 2-µm design rule combined with the double-level polysilicon layer allowed for layout of the NMOS memory cell in 266.5 µm2and design of the die in 34.3 mm2.

Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs

In order to take full advantage of VLSI, new design methods are necessary to improve the yield and testability. Designs which incorporate redundancy to improve the yields of high density memory chips are well known. The goal of this paper is to motivate the extension of this technique to other types of VLSI logic circuits. The benefits and the limitations of on-chip modularization and the use of spare elements are presented, and significant yield improvements are shown to be possible.

A novel associative approach for fault-tolerant MOS RAMs

A novel associative iterative approach providing unique advantages is developed to increase yield of large capacity, 16K bit-1M bit, semiconductor random access memories. The circuit implementation has minimum effect on performance and on the original design of the memory. The increase in access time and power dissipation is less than 2 and 0.6 percent, respectively. The flexibility of this concept allows for organization of redundant elements in blocks, rows, columns, clusters, or bits and to locate the redundancy anywhere on the chip. A wide range of programmable elements, e.g., fusable links, laser programmable cells, and content addressable memory units, are applicable. The amount of spare elements can be optimized to achieve a maximum effective yield of as much as 85 percent. The increase in active circuit area is a function of defect density and memory capacity. The redundancy control and spare memories can be added to memories as modules without modifications of the original designs. The circuits discussed here are for CMOS/SOS radiation hardened application; the concepts, however, can be applied to bulk silicon MOS technologies as well.

Military requirements for water supply

The U.S. Army Mobility Equipment Research and Development Command is developing transportable reverse osmosis (RO) equipment to produce potable water from fresh, brackish and sea water sources and to remove chemical and radiological contaminants from these waters. Of the various water purification processes available the Army has determined that reverse osmosis has the greatest potential for achieving this multi-purpose function. A 600 gallon per hour (gph) trailer mounted unit, the smallest unit in a family of equipment to be developed, has undergone field testing producing potable water at rated capacity from the turbid Potomac River, a brackish well supply, and the Atlantic Ocean. In addition, the unit has successfully removed three toxic chemical agents from a natural water source. Principle components of the unit are a multi-media filter using the addition of cationic polyelectrolyte to aid preclarification of the water and 10 pressure vessels containing 20 spiral wound reverse osmosis elements. Special dry cellulose acetate membranes have been developed that have been found successful on fresh and brackish water operations in which the feed water is prechlorinated. The CA elements are wet-dry reversible so that the unit may be completely drained for transport and freezing environments. Replacement or spare elements may be stored in a dry condition without impairing membrane performance. In addition, a physically interchangeable dry polyamide (PA-300) RO element has been successfully used to produce drinking water in a single pass from sea water.

Insight into Standby Redundancy via Unreliability

Standby redundancy is the oldest form of redundancy using switches. After a failure of the working element, an identical spare is substituted by switching. Unfortunately, the Coverage (the probability of a successful reconfiguration) of the system is always less than unity and, furthermore, the spare element might fail before it is switched in. Using, certain assumptions, this paper provides simple formulae for the reliability of a standby system. Criteria for the Coverage and the best number of standby elements are presented. Simple expressions for a Mission Time Improvement Factor are derived. A general discussion of standby redundancy is given to place the assumptions in proper perspective.